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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
VII
Address = 4Fh, Rx CP Interrupt Status Register ........................................................................................ 99
Bit 2—OAM (Cell Received) Interrupt Status .............................................................................................. 99
Bit 1—LCD (Loss of Cell Delineation) Interrupt Status .............................................................................. 99
Bit 0—HEC Byte Error Interrupt Status ..................................................................................................... 100
Address = 50h, Rx CP Idle Cell Pattern Header—Byte 1 .......................................................................... 100
Address = 51h, Rx CP Idle Cell Pattern Header—Byte 2 .......................................................................... 100
Address = 52h, Rx CP Idle Cell Pattern Header—Byte 3 .......................................................................... 100
Address = 53h, Rx CP Idle Cell Pattern Header—Byte 4 .......................................................................... 101
Address = 54h, Rx CP Idle Cell Mask Header—Byte 1 ............................................................................. 101
Address = 55h, Rx CP Idle Cell Mask Header—Byte 2 ............................................................................. 102
Address = 56h, Rx CP Idle Cell Mask Header—Byte 3 ............................................................................. 102
Address = 57h, Rx CP Idle Cell Mask Header—Byte 4 ............................................................................. 102
Address = 58h, Rx CP User Cell Filter Pattern Header—Byte 1 .............................................................. 103
Address = 59h, Rx CP User Cell Filter Pattern Header—Byte 2 .............................................................. 103
Address = 5Ah, Rx CP User Cell Filter Pattern Header—Byte 3 ............................................................. 104
Address = 5Bh, Rx CP User Cell Filter Pattern Header—Byte 4 ............................................................. 104
Address = 5Ch, Rx CP User Cell Filter Mask Header—Byte 1 ................................................................. 104
Address = 5Dh, Rx CP User Cell Filter Mask Header—Byte 2 ................................................................. 105
Address = 5Eh, Rx CP User Cell Filter Mask Header—Byte 3 ................................................................. 105
Address = 5Fh, Rx CP User Cell Filter Mask Header—Byte 4 ................................................................. 106
Address = 60h, Tx CP Control Register ..................................................................................................... 106
Bit 7—Scrambler Enable ............................................................................................................................. 106
Bit 6—Coset Enable .................................................................................................................................... 106
Bit 5—HEC Byte Insert Enable—Assigned Cells ...................................................................................... 106
Bit 4—TDPChk Pat (Transmit Data Path Integrity Check Pattern Selection) ......................................... 107
Bit 3—GFC Nibble-Field Insert Enable ...................................................................................................... 107
Bit 2—TDP (Transmit Data Path Integrity Test) Error Interrupt Enable .................................................. 107
Bit 1—IC (Idle Cell) HEC Byte Calculation Enable .................................................................................... 107
Bit 0—TDP (Transmit Data Path Integrity Check) Error Interrupt Status ............................................... 107
Address = 61h, Tx CP OAM Cell Register ................................................................................................. 108
Bit 7—Send OAM (Cell) ............................................................................................................................... 108
Address = 62h, Tx CP HEC Byte Error Mask Register ............................................................................. 108
Address = 63h, Future Use ......................................................................................................................... 108
Address = 64h, Tx CP Idle Cell Pattern Header—Byte 1 .......................................................................... 108
Address = 65h, Tx CP Idle Cell Pattern Header—Byte 2 .......................................................................... 109
Address = 66h, Tx CP Idle Cell Pattern Header—Byte 3 .......................................................................... 109
Address = 67h, Tx CP Idle Cell Pattern Header—Byte 4 .......................................................................... 109
Address = 68h, Tx CP Idle Cell Pattern Header—Byte 5 .......................................................................... 109
Address = 69h, Tx CP Idle Cell Payload Register ..................................................................................... 110
Address = 6Ah, UTOPIA Configuration Register ...................................................................................... 110
Bit 5—Handshake Mode .............................................................................................................................. 110
Bit 4—M-PHY/S-PHY* (UTOPIA Operating Mode) ..................................................................................... 110
Bit 3—CellOf52Bytes ................................................................................................................................... 110
Bits 2, 1,—TFIFODepth[1, 0] ....................................................................................................................... 111