
á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
57
35h
PMON Received Valid Cell Count— LSB
R/O
36h
PMON Discarded Cell Count—MSB
R/O
37h
PMON Discarded Cell Count—LSB
R/O
38h
PMON Transmitted Idle Cell Count—MSB
R/O
39h
PMON Transmitted Idle Cell Count—LSB
R/O
3Ah
PMON Transmitted Valid Cell Count—
MSB
R/O
3Bh
PMON Transmitted Valid Cell Count—
LSB
R/O
3Ch
PMON Holding Register
R/O
3Dh
One Second Error Status Register
R/O
3Eh
LCV—One Second Accumulator
Register—MSB
R/O
3Fh
LCV—One Second Accumulator
Register—LSB
R/O
40h
Frame Parity Error—One Second
Accumulator Register —MSB
R/O
41h
Frame Parity Error—One Second
Accumulator Register—LSB
R/O
42h
HEC Errors—One Second Accumulator
Register—MSB
R/O
43h
HEC Errors—One Second Accumulator
Register—LSB
R/O
44h
Rx PLCP Configuration/Status Register
Rx PLCP Configuration/Status Register
(R/W Portion only)
Combination of R/O
and R/W
45h
Rx PLCP Interrupt Enable Register
Rx PLCP Interrupt Enable Register
(R/W Portion only)
Combination of R/O
and R/W
46h
Rx PLCP Interrupt Status Register
Combination of R/O
and RUR
47h
Future Use
Future Use
—
48h
Tx PLCP A1 Byte Error Mask
Tx PLCP A1 Byte Error Mask
R/W
49h
Tx PLCP A2 Byte Error Mask
Tx PLCP A2 Byte Error Mask
R/W
4Ah
Tx PLCP BIP-8 Error Mask
Tx PLCP BIP-8 Error Mask
R/W
4Bh
Tx PLCP G1 Byte Register
Tx PLCP G1 Byte Register (R/W
portion only)
Combination of R/O
and R/W
4Ch
Rx CP Configuration Register
Rx CP Configuration Register (R/W
portion only)
Combination of R/O
and R/W
4Dh
Rx CP Additional Configuration Register
Rx CP Additional Configuration
Register (R/W portion only)
Combination of R/O
and R/W
4Eh
Rx CP Interrupt Enable Register
Rx CP Interrupt Enable Register (R/W
portion only)
Combination of R/O
and R/W
T
ABLE
4: R
EGISTER
A
DDRESSING
OF
THE
UNI P
ROGRAMMABLE
R
EGISTERS
(C
ONT
’
D
)
A
DDRESS
R
EAD
M
ODE
R
EGISTER
W
RITE
M
ODE
R
EGISTER
R
EGISTER
T
YPE