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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
281
Note:
regarding Figure 90
1. The Receive UTOPIA Data bus is configured to be
16 bits wide. Hence, the data, which the Receive
UTOPIA Interface block places on the Receive
UTOPIA Data bus, is expressed in terms of 16-bit
words: (e.g., W0–W26).
2. The Receive UTOPIA Data bus is configured to
handle 54 bytes/cell. Hence, Figure 90 illustrates
the ATM Layer processor reading 27 words (W0
through W26) for each ATM cell.
3. The Receive UTOPIA Interface block is configured
to operate in the Cell Level Handshake mode.
Note:
regarding Figure 91
1. The Receive UTOPIA Data bus is configured to be
16 bits wide. Hence, the data, which the ATM Layer
processor places on the Transmit UTOPIA Data
bus, is expressed in terms of 16 bit words: (e.g.,
W0–W26).
2. The Receive UTOPIA Interface block is configured
to handle 54 bytes/cell. Hence, Figure 91 illustrates
the ATM Layer processor reading 27 words (W0
through W26) for each ATM cell.
3. The Receive UTOPIA Interface block is configured
to operate in the Octet-Level Handshaking Mode.
F
IGURE
90. T
IMING
D
IAGRAM
OF
ATM L
AYER
PROCESSOR
R
ECEIVING
D
ATA
FROM
THE
UNI
OVER
THE
UTOPIA
D
ATA
B
US
, (S
INGLE
-PHY M
ODE
/C
ELL
L
EVEL
H
ANDSHAKING
).
RxClk
RxClav
RxEnB*
RxData[15:0]
RxSoC
W24
W25
W26
W0
W1
W2
W25
W26
1
2
3
4
5
6
7
8
9
31
32
34
F
IGURE
91. T
IMING
D
IAGRAM
OF
ATM L
AYER
PROCESSOR
R
ECEIVING
D
ATA
FROM
THE
UNI
OVER
THE
UTOPIA
D
ATA
B
US
, (S
INGLE
-PHY M
ODE
/O
CTET
L
EVEL
H
ANDSHAKING
).
RxClk
RxClav
RxEnB*
RxData[15:0]
RxSoC
W2
W3
W4
X
W1
W0
1
2
3
4
5
6
7
8
9
10
11
12