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參數(shù)資料
| 型號(hào)： | V59C1G01808QBLF-19A |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁(yè)數(shù)： | 75/80頁(yè) |
| 文件大?。?/td> | 971K |
| 代理商： | V59C1G01808QBLF-19A |
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ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
V59C1G01(408/808)QB Rev. 1.1 December 2008
tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.
- tJIT(cc), tJIT(cc,lck)
tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles:
tJIT(cc) = Max of |tCKi+1 – tCKi|
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.
tERR (2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)
tERR is defined as the cummulative error across multiple consecutive cycles from tCK (avg).
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