參數(shù)資料
型號： V59C1G01808QBLF-19A
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： DDR DRAM, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁數(shù)： 19/80頁
文件大?。?/td> 971K
代理商： V59C1G01808QBLF-19A
26
V59C1G01(408/808)QB Rev. 1.1 December 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that define how the burst mode will operate are burst
sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst
mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for
ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the
MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3)
of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write oper-
ation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when
burst length = 8 is used, see the “Burst Interruption “ section of this datasheet. A Burst Stop command is not
supported on DDR2 SDRAM devices.
Burst Length and Sequence
Bu rs t L ength
Starting Address
(A2 A1 A0)
Seque nt ial A ddr essing (decim al)
Interleave Addressi ng (decimal)
4
x 0 0
0, 1, 2, 3
x 0 1
1, 2, 3, 0
1, 0, 3, 2
x 1 0
2, 3, 0, 1
x 1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0, 1, 2, 3, 4, 5, 6, 7
0 0 1
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
0 1 0
2, 3, 0, 1, 6, 7, 4, 5
0 1 1
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1 0 0
4, 5, 6, 7, 0, 1, 2, 3
1 0 1
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1 1 0
6, 7, 4, 5, 2, 3, 0, 1
1 1 1
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Note: 1) Page length is a function of I/O organization
128Mb X 4 organization (CA0-CA9, CA11); Page Length = 1 kByte
64Mb X 8 organization (CA0-CA9 ); Page Length = 1 kByte
2) Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR
or DDR components
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