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參數(shù)資料
| 型號： | V59C1G01808QBLF-19A |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 49/80頁 |
| 文件大?。?/td> | 971K |
| 代理商： | V59C1G01808QBLF-19A |
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ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
V59C1G01(408/808)QB Rev. 1.1 December 2008
Asynchronous CKE Low Event
DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE
asynchronously drops “l(fā)ow” during any valid operation DRAM is not guaranteed to preserve the contents of
the memory array. If this event occurs, the memory controller must satisfy a time delay ( tdelay ) before turn-
ing off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised “high” again. The
DRAM must be fully re-initialized as described the the initialization sequence starting with step 4.
The DRAM is ready for normal operation after the initialization sequence. The minimum time clocks needs
to be ON after CKE asynchronously drops low (the tdelay timing parameter) is equal to tIS + tCK + tIH.
Asynchronous CKE Low Event
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
tdelay
CK, CK
stable clocks
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