參數(shù)資料
型號(hào)： V59C1G01808QBLF-19A
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： DDR DRAM, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁(yè)數(shù)： 70/80頁(yè)
文件大?。?/td> 971K
代理商： V59C1G01808QBLF-19A
72
V59C1G01(408/808)QB Rev. 1.1 December 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
AC Characteristics (AC operating conditions unless otherwise noted)
Parameter
Symbol
(DDR2-533)
-37
(DDR2-667)
-3
(DDR2-800)
-25A
(DDR2-800)
-25
(DDR2-1066)
-19A
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Row Cycle Time
tRC
60
-
60
-
60
-
57.5
-
58.125
-
ns
Auto Refresh Row Cycle
Time
tRFC
127.5
-
127.5
-
127.5
-
127.5
-
127.5
-
ns
11
Row Active Time
tRAS
45
70K
45
70K
45
70K
45
70K
45
70K
ns
21
Row Address to Column Ad-
dress Delay
tRCD
15
-
15
-
15
-
12.5
-
13.125
-
ns
20
Row Active to Row Active
Delay
tRRD
7.5
-
7.5
-
7.5
-
7.5
-
7.5
-
ns
Four Activate Window for
tFAW
37.5
-
37.5
-
35
-
35
-
35
-
ns
Column Address to Column
Address Delay
tCCD
2
-
2
-
2
-
2
-
2
-
CLK
Row Precharge Time
tRP
15
-
15
-
15
-
12.5
-
13.125
-
ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
-
15
-
ns
Auto Precharge Write Re-
covery + Precharge Time
tDAL
tWR +tRP
-
tWR +tRP
-
tWR +tRP
-
tWR +tRP
-
tWR +tRP
-
ns
12
System
Clock
Cycle
Time
CAS Latency = 3
tCK
5
8
5
8
------
ns
2
CAS Latency = 4
3.75
8
3.75
8
3.75
8
3.75
8
-
ns
2
CAS Latency = 5
-
3
8
3
8
2.5
8
3
8
ns
2
CAS Latency = 6
-
2.5
8
2.5
8
2.5
8
ns
2
CAS Latency = 7
-
----
1.875
8
ns
2
Clock High Level Width
tCH
0.45
0.55
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
CLK
Clock Low Level Width
tCL
0.45
0.55
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
CLK
Data-Out edge to Clock
edge Skew
tAC
-0.5
0.45
-0.45
0.45
-0.40
0.40
-0.40
0.40
-0.35
0.35
ns
DQS-Out edge to Clock
edge Skew
tDQSCK
-0.45
0.40
-0.40
0.40
-0.35
0.35
-0.35
0.35
-0.325
0.325
ns
DQS-Out edge to Data-Out
edge Skew
tDQSQ
-
0.30
-
0.24
-
0.20
-
0.20
-
0.175
ns
Data-Out hold time from
DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
Data hold skew factor
tQHS
-
400
-
340
-
300
-
300
-
250
ps
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns
5
Input Setup Time (fast slew
rate)
tIS
250
-
200
-
175
-
175
-
125
-
ps
15,17
Input Hold Time (fast slew
rate)
tIH
375
-
275
-
250
-
250
-
200
-
ps
15,17
Input Pulse Width
tIPW
0.60
-
0.60
-
0.60
-
0.60
-
0.60
-
CLK
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