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| 型號(hào)： | V59C1G01808QBLF-19A |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁(yè)數(shù)： | 4/80頁(yè) |
| 文件大小： | 971K |
| 代理商： | V59C1G01808QBLF-19A |
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V59C1G01(408/808)QB Rev. 1.1 December 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
Address Field
Extended Mode Register(2)
0*1
BA0 A15 *2 ~ A13
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
*1 BA0 , BA1, and BA2 must be programmed to 0 when setting the mode register during initialization.
BA1
1
EMRS(2) Programming:
*1
A12
Address Field
Extended Mode Register(3)
*1 : EMRS(3) is reserved for future use and all bits except BA0, BA1, BA2 must be programmed to 0 when setting
the mode register during initialization.
*2 : A14 and A15 is reserved for future usage.
EMRS(3) Programming: Reserved*1
0 *2
BA2
0
0*1
BA0 A15 *2 ~ A13
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
BA1
1
A12
0 *2
BA2
0
PASR
The PASR bits allows the user to dynamically customize the memory array size to the actual needs. This feature
allows the device to reduce standby current by refreshing only the memory arrays that contain essential
data.The refresh options are full array, one-half array, one-quarter array, three-fourth array, or none of the array.
The mapping of these partitions can start at either the beginning or the end of the address map. Please see
the following table.
PASR
P ASR[2]
ACTIVE SECTION
00
0
Full array
0
1
1/2 array (Banks 0,1, 2, 3)
0
1
0
1/4 array (Bank 0, 1)
0
1
1/8 array (Bank 0)
1
0
3/4 array (Banks 2,3,4,5,6,7)
1
0
1
1/2 array (Banks 4, 5, 6, 7)
1
0
1/4 array (Bank 6,7)
1
1/8 array (Bank 7)
P ASR[1]
P ASR[0]
*2 : A14 and A15 is reserved for future usage.
A7
High Temperature Self Refresh rate enable
0
1
Commercial temperature default
Industrial temperature option:
use if Tc exceeds 85 C
o
*3 : At tOPER 85 C, Double refresh rate (tREFI: 3.9us) is required, and to enter self refresh mode
at this temperature range it must be required an EMRS command to change itself refresh rate.
O
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