參數(shù)資料
型號(hào)： V59C1G01808QBLF-19A
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： DDR DRAM, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁數(shù)： 72/80頁
文件大?。?/td> 971K
代理商： V59C1G01808QBLF-19A
74
V59C1G01(408/808)QB Rev. 1.1 December 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
Exit Precharge Power Down
to any non-Read Command
tXP
2
-
2
-
2-
3
-
CLK
14
Exit Active Power Down to
Read Command
tXARD
2
-
2
-
2-
3
-
CLK
Exit Active Power Down to
Read Command (Slow exit,
Lower Power)
tXARDS
7-AL
-
7-AL
-
8-AL
-
8-AL
-
10-AL
-
CLK
Minimum time clocks re-
mains ON after CKE asyn-
chronously drops LOW
tDelay
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
ns
CKE minimum high and low
pulse width
tCKE
3
-
3
-
3
-
3
-
3
-
CLK
Average Periodic Refresh In-
terval 0C < T < 85C
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
us
18
Period jitter
tJITPER
-125
125
-125
125
-100
100
-100
100
-90
90
ps
22
Half period
tJITDTY
-125
125
-125
125
-100
100
-100
100
-75
75
ps
22
Cycle to Cycle
tJITCC
-250
250
-250
250
-200
200
-200
200
-180
180
ps
22
Cumulative error, 2 cycles
tERR(2PER)
-175
175
-175
175
-150
150
-150
150
-132
132
ps
22
Cumulative error, 3 cycles
tERR(3PER)
-225
225
-225
225
-175
175
-175
175
-157
157
ps
22
Cumulative error, 4 cycles
tERR(4PER)
-250
250
-250
250
-200
200
-200
200
-175
175
ps
22
Cumulative error, 5 cycles
tERR(5PER)
-250
250
-250
250
-200
200
-200
200
-188
188
ps
22
Cumulative error, 6-10 cy-
cles
tERR(6-
10PER)
-350
350
-350
350
-300
300
-300
300
-250
250
ps
22
Cumulative error, 11-50 cy-
cles
tERR(11-
50PER)
-450
450
-450
450
-450
450
-450
450
-425
425
ps
22
Parameter
Symbol
(DDR2-533)
-37
(DDR2-667)
-3
(DDR2-800)
-25A
(DDR2-800)
-25
(DDR2-1066)
-19A
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
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V62/07602-03XE 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 3 V, PDSO6
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