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| 型號： | V59C1G01808QBLF-19A |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 45/80頁 |
| 文件大?。?/td> | 971K |
| 代理商： | V59C1G01808QBLF-19A |
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5
ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
V59C1G01(408/808)QB Rev. 1.1 December 2008
Signal Pin Description
Pin
Type
Function
CK
Input
The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK.
CKE
Input
Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the
Power Down mode, or the Self Refresh mode.
CS
Input
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
RAS, CAS WE
Input
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be
executed by the SDRAM.
A0 - A13
Input
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled
at the rising clock edge for x4 and x8 devices.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled
at the rising clock edge.CAn depends on the SDRAM organization:
128M x 4 DDR CAn = CA9, A11
64M x 8 DDR CAn = CA9
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1, BA2 defines the
bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0, BA1and BA2 to control
which bank(s) to precharge. If A10 is high, all eight banks will be precharged simultaneously regardless
of state of BA0 , BA1 and BA2.
BA0-BA2
Input
Selects which bank is to be active.
DQx
LDQx
Input/
Output
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQ0-DQ3 for x4 component, DQ0-DQ7 for x8 component and LDQ0-LDQ7.
DQS,(DQS)
LDQS,(LDQS)
RDQS,(RDQS)
Input/
Output
Data Strobe, output with read data, input with write data. Edge-aligned with read data, centered in write
data. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing.
The data strobes DQS, LDQS, and RDQS may be used in single ended mode or paired with optional
complimentary signals DQS, LDQS, and RDQS to provide differential pair signaling to the system dur-
ing both reads and writes. AN EMRS(1) control bit enables or disables all complementary data strobe
signals.
DM,
LDM,UDM
Input
In Write mode, DM operates as a word mask by allowing input data to be written if it is low but blocks
the write operation.
VDD,VSS
Supply
Power and ground for the input buffers and the core logic.
VDDQ VSSQ
Supply
Isolated power supply and ground for the output buffers to provide improved noise
immunity. 1.8V +/- 0.1V
VREF
Input
SSTL Reference Voltage for Inputs
VDDLQ VSSDL
Supply
Isolated power supply and ground for the DLL to provide improved noise
immunity. 1.8V +/- 0.1V
ODT
Input
On Die Termination Enable. It enables termination resistance internal to the DRAM. ODT is applied to
each DQ, DQS, DQS and DM signals for x4 component and DQ, DQS, DQS, RDQS, RDQS and DM
for the x8 component. ODT will be ignored if EMRS disable the function.
RFU
Reserved for future use
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