參數(shù)資料
型號(hào)： V59C1G01808QBLF-19A
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： DDR DRAM, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁(yè)數(shù)： 71/80頁(yè)
文件大?。?/td> 971K
代理商： V59C1G01808QBLF-19A
73
ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
V59C1G01(408/808)QB Rev. 1.1 December 2008
Write DQS High Level Width
tDQSH
0.35
CLK
Write DQS Low Level Width
tDQSL
0.35
CLK
CLK to First Rising edge of
DQS-In
tDQSS
-0.25
tCK
+0.25
tCK
-0.25
tCK
+0.25
tCK
-0.25
tCK
+0.25
tCK
-0.25
tCK
+0.25
tCK
-0.25
tCK
+0.25
tCK
CLK
Data-In Setup Time to DQS-
In (DQ & DM) Differential
tDS
100
-
100
-
50
-
50
-
0
-
ps
16,17,
18
Data-in Hold Time to DQS-In
(DQ & DM) Differential
tDH
225
-
175
-
125
-
125
-
75
-
ps
16,17,
18
DQS falling edge to CLK ris-
ing Setup Time
tDSS
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
CLK
DQS falling edge from CLK
rising Hold Time
tDSH
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
CLK
DQ & DM Input Pulse Width
tDIPW
0.35
-
0.35
-
0.35
-
0.35
-
0.35
-
CLK
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CLK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Preamble Setup
Time
tWPRES
0
-
0
-
0
-
0
-
0
-
CLK
Write DQS Preamble Hold
Time
tWPREH
0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
CLK
Write DQS Preamble Time
tWPRE
0.35
-
0.35
-
0.35
-
0.35
-
0.35
-
CLK
10
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
10
Internal read to precharge
command delay
tRTP
7.5
-
7.5
-
7.5
-
7.5
-
7.5
-
ns
Internal write to read com-
mand delay
tWTR
7.5
-
7.5
-
7.5
-
7.5
-
7.5
-
ns
13
Data out high impedance
time from CLK/CLK
tHZ
-
tAC(max)
-
tAC(max)
-
tAC(max)
-
tAC(max)
-
tAC(max)
ns
7
DQS/DQS low impedance
time from CLK/CLK
tLZ(DQS)
tAC(min) tAC(max) tAC(min) tAC(max) tAC(min) tAC(max) tAC(min) tAC(max) tAC(min) tAC(max)
ns
7
DQ low impedance time from
CLK/CLK
tLZ(DQ)
2xtAC(min) tAC(max) 2xtAC(min) tAC(max) 2xtAC(min) tAC(max) 2xtAC(min) tAC(max) 2xtAC(min) tAC(max)
ns
7
Mode Register Set Delay
tMRD
2-
2
-
2
-
2
-
CLK
9
MRS command to ODT up-
date delay
tMOD
012012
0
12
0
12
0
12
ns
OCD drive mode output de-
lay
tOIT
012012
0
12
0
12
0
12
ns
Exit Self Refresh to Non-
Read Command
tXSNR
tRFC+10
-
tRFC+10
-
tRFC+10
-
tRFC+10
-
tRFC+10
-
ns
19
Exit Self Refresh to Read
Command
tXSRD
200
-
200
-
200
-
200
-
200
-
CLK
Parameter
Symbol
(DDR2-533)
-37
(DDR2-667)
-3
(DDR2-800)
-25A
(DDR2-800)
-25
(DDR2-1066)
-19A
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
V5F110BB3 SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.5A, 125VDC, 2.4mm, PANEL MOUNT
V62/07602-02XE 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 2.5 V, PDSO6
V62/07602-03XE 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 3 V, PDSO6
V62C2162048LL-100T 128K X 16 STANDARD SRAM, 100 ns, PDSO44
V62C2162048L-45T 128K X 16 STANDARD SRAM, 45 ns, PDSO44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V5A010CB 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER
V5A010CB 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER
V5A010CB4D 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER
V5A010CB4D 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER
V5A010CB4E 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*