參數(shù)資料
型號： SAA5667HL/NNNN
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù)： 80/112頁
文件大?。?/td> 537K
代理商： SAA5667HL/NNNN
2004 Sep 03
7
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
6.2
Pin description
Table 1
LQFP100 package
SYMBOL
PIN
TYPE
DESCRIPTION
P2.0/TPWM
100
I/O
Port 2. 8-bit programmable bidirectional port with alternative functions.
P2.0/TPWM is the output for the 14-bit high precision PWM; P2.1/PWM0 to
P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6.
P2.1/PWM0
93
I/O
P2.2/PWM1
94
I/O
P2.3/PWM2
95
I/O
P2.4/PWM3
96
I/O
P2.5/PWM4
97
I/O
P2.6/PWM5
98
I/O
P2.7/PWM6
1
I/O
P3.0/ADC0
2
I/O
Port 3. 8-bit programmable bidirectional port with alternative functions.
P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility and
P3.4/PWM7 is the output for the 6-bit PWM7; P3.4/PWM7/T2EX is the
output for the 6-bit PWM7 or the Timer 2 control; P3.5/INT5 is the external
Interrupt 5; P3.6 and P3.7 have no alternative functions.
P3.1/ADC1
4
I/O
P3.2/ADC2
5
I/O
P3.3/ADC3
6
I/O
P3.4/PWM7/T2EX
44
I/O
P3.5/INT5
54
I/O
P3.6
59
I/O
P3.7
25
I/O
VSSC
11, 62, 99
core ground
P0.0/RX
16
I/O
Port 0. 8-bit programmable bidirectional port (with alternative functions).
P0.0/RX and P0.1/TX are respectively the serial transmit and receive lines
for the UART; P0.2/INT2 to P0.4/INT4 are the external interrupts 2 to 4;
P0.5 and P0.6 have no alternative functions and have 8 mA current sinking
capability for direct drive of LEDs.
P0.1/TX
17
I/O
P0.2/INT2
18
I/O
P0.3/INT3
22
I/O
P0.4/INT4
24
I/O
P0.5
13
I/O
P0.6
28
I/O
P0.7/T2
29
I/O
VSSA
30
analog ground
CVBS0
31
I
2 composite video input selectable via SFR; a positive-going 1 V
(peak-to-peak) input is required, connected via a 100 nF capacitor
CVBS1
32
I
SYNC_FILTER
34
I/O
CVBS sync lter input; this pin should be connected to VSSA via a 100 nF
capacitor.
IREF
35
I
Reference current input for analog circuits, connected to VSSA via a 24 k
resistor.
FRAME
41
O
De-interlace output synchronized with the VSYNC pulse to produce a
non-interlaced display by adjustment of the vertical deection circuits.
VPE
21, 42
I
OTP programming voltage
COR
43
O
Open-drain, active LOW output which allows selective contrast reduction of
the TV picture to enhance a mixed mode display.
VDDA
45
+3.3 V analog power supply
B
46
O
pixel rate output of the BLUE colour information
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