參數(shù)資料
型號(hào)： SAA5667HL/NNNN
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 26/112頁(yè)
文件大?。?/td> 537K
代理商： SAA5667HL/NNNN
2004 Sep 03
20
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
Port 0 Conguration A (P0CFGA) and Port 0 Conguration B (P0CFGB)
P0CFGA<7:0> and P0CFGB<7:0> These two registers are used to congure Port 0 lines. For example, the
conguration of Port 0 pin 3 is controlled by setting bit 3 in both P0CFGA and
P0CFGB. P0CFGB<x>/P0CFGA<x>:
00 = P0.x in Mode 0 (open-drain)
01 = P0.x in Mode 1 (quasi-bidirectional)
10 = P0.x in Mode 2 (high-impedance)
11 = P0.x in Mode 3 (push-pull)
Port 1 Conguration A (P1CFGA) and Port 1 Conguration B (P1CFGB)
P1CFGA<7:0> and P1CFGB<7:0> These two registers are used to congure Port 1 lines. For example, the
conguration of Port 1 pin 3 is controlled by setting bit 3 in both P1CFGA and
P1CFGB. P1CFGB<x>/P1CFGA<x>:
00 = P1.x in Mode 0 (open-drain)
01 = P1.x in Mode 1 (quasi-bidirectional)
10 = P1.x in Mode 2 (high-impedance)
11 = P1.x in Mode 3 (push-pull)
Port 2 Conguration A (P2CFGA) and Port 2 Conguration B (P2CFGB)
P2CFGA<7:0> and P2CFGB<7:0> These two registers are used to congure Port 2 lines. For example, the
conguration of Port 2 pin 3 is controlled by setting bit 3 in both P2CFGA and
P2CFGB. P2CFGB<x>/P2CFGA<x>:
00 = P2.x in Mode 0 (open-drain)
01 = P2.x in Mode 1 (quasi-bidirectional)
10 = P2.x in Mode 2 (high-impedance)
11 = P2.x in Mode 3 (push-pull)
Port 3 Conguration A (P3CFGA) and Port 3 Conguration B (P3CFGB)
P3CFGA<7:0> and P3CFGB<7:0> These two registers are used to congure Port 3 lines. For example, the
conguration of Port 3 pin 3 is controlled by setting bit 3 in both P3CFGA and
P3CFGB. P3CFGB<x>/P3CFGA<x>:
00 = P3.x in Mode 0 (open-drain)
01 = P3.x in Mode 1 (quasi-bidirectional)
10 = P3.x in Mode 2 (high-impedance)
11 = P3.x in Mode 3 (push-pull)
Power Control Register (PCON)
SMOD
UART baud rate double control
ARD
auxiliary RAM disable, all MOVX instructions access the external data memory
RFI
disable ALE during internal access to reduce radio frequency Interference
WLE
Watchdog Timer enable
GF1
general purpose ag
GF0
general purpose ag
PD
Power-down activation bit
IDL
Idle mode activation bit
BITS
FUNCTION
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