參數(shù)資料
型號(hào)： SAA5667HL/NNNN
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 79/112頁(yè)
文件大?。?/td> 537K
代理商： SAA5667HL/NNNN
2004 Sep 03
69
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
23.3
Display timing modes
The display can be configured for either 50/60 Hz or 100/120 Hz (2H/2V only) using the display configuration
MMR 87FFH.
Table 27 Display timing modes
DISPLAY TIMING
(MMR 87FFH)
SUPPORTED
HSYNC/VSYNC RATE
DISPLAY CLOCK
NUMBER OF CHARACTERS
100 HZ BIT
TWO_PAGE BIT
0
1H/1V
12 MHz
40 (single window)
X
1
1H/1V
24 MHz
80 (double window)
1
0
1H/1V; 2H/2V
24 MHz
40 (single window)
23.3.1
DOUBLE WINDOW OPERATION
This mode enables two different pages to be displayed
side-by-side for use with 16:9 TV screens. The display
section clock runs at 24 MHz in this mode. Fig.26 shows
the combination of two page display possible on the
SAA56xx device.
Two page mode is selected using MMR 87FFH bit 0. The
two pages displayed are separated by two character
spaces to allow the display logic to switch correctly from
one window to the other. The facility is restricted to 1H/1V
(i.e. 50/60Hz display TVs).
Two control bits exist in double window mode to select
Closed Caption display or text display in each window:
TXT21.CC/TXT for Page A and TXT28.CC_TXT B for
Page B.
TXT: When displaying two Teletext pages side by side, the
memory block being displayed in Page A is selected using
SFR TXT14<3:0> and for Page B using SFR TXT28<3:0>.
The Data Capture section writes the header and time
information only to the memory block corresponding to the
active page. This active page is determined with the
TXT28.ACTIVE PAGE bit. When set to logic 0, Page A is
active, set to logic 1, Page B is active.
Operation of the REVEAL bit (TXT7.5) and CURSOR ON
bit (TXT7.6) only affects the active page.
CC: When CC display mode is selected in two page mode,
only one window may be used for CC/OSD and the other
either Text or Video. Two page CC display (either captions
or OSD) side-by-side is not possible because there is only
one area of memory available for the CC data.
23.3.2
SINGLE WINDOW OPERATION
At reset, the device defaults to single window mode, which
corresponds to 87FFH bit 0 set to logic 0. In this mode, the
settings applying to the window displayed are those that
would apply to Page A in double window mode.
For 2H/2V display TVs, the 100 Hz bit, MMR 87FFH bit 1,
must be set to logic 1 to fit a whole display window.
For 1H/1V display TVs, when MMR 87FFH bit 1 is set to
logic 0, the display window occupies the whole screen,
whereas if MMR 87FFH bit 1 is set to logic 1, only half the
screen would be occupied by the display window. This
latter configuration would give the same kind of display as
in the double window mode with Page A: CC or
Text Page B: Video.
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