參數(shù)資料
型號: SAA5667HL/NNNN
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù): 54/112頁
文件大?。?/td> 537K
代理商: SAA5667HL/NNNN
2004 Sep 03
46
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
16.3.3
SAD DC COMPARATOR MODE
The SAD module (see Fig.11) incorporates a DC
Comparator mode, which is selected using the
‘DC_COMP’ control bit in the SADB SFR. This mode
enables the microcontroller to detect a threshold crossing
at the input to the selected analog input pin
(P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) of
the software ADC. A level sensitive interrupt is generated
when the analog input voltage level at the pin falls below
the analog output level of the SAD DAC.
This mode is intended to provide the device with a
wake-up mechanism from Power-down or Idle mode when
a key-press on the front panel of the TV is detected.
The following software sequence should be used when
utilizing this mode for Power-down or Idle mode:
1. Disable INT1 using the IEN0 SFR.
2. Set INT1 to level sensitive using the TCON SFR.
3. Set the DAC digital input level to the desired threshold
level using SAD/SADB SFRs and select the required
input pin (P3.0, P3.1, P3.2 or P3,3) using CH1 and
CH0 in the SAD SFR.
4. Enter DC Compare mode by setting the ‘DC_COMP’
enable bit in the SADB SFR.
5. Enable INT1 using the IEN0 SFR.
6. Enter Power-down/Idle mode. Upon wake-up, the
SAD should be restored to its conventional operating
mode by disabling the ‘DC_COMP’ control bit.
handbook, halfpage
MBK960
MUX
4 : 1
ADC0
ADC1
ADC2
ADC3
CH<1:0>
SAD<3:0>
SADB<3:0>
VDDP
VHI
8-BIT
DAC
Fig.11 SAD block diagram.
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