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參數資料
| 型號： | SAA5667HL/NNNN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數： | 65/112頁 |
| 文件大?。?/td> | 537K |
| 代理商： | SAA5667HL/NNNN |
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2004 Sep 03
56
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
22.1.1
CVBS SWITCH
The CVBS switch is used to select the required analog
input, depending on the value of TXT8.CVBS1/CVBS0.
22.1.2
ANALOG-TO-DIGITAL CONVERTER
The output of the CVBS switch is passed to a
Differential-to-Single-Ended Converter (DIVIS, not shown
in Fig.17), although here it is used in single-ended
configuration with a reference. A full-flash ADC with a
sampling rate of 12 MHz converts the analog output of the
DIVIS to a digital representation.
22.1.3
MULTI-RATE VIDEO INPUT PROCESSOR (MULVIP)
The MulVIP (used for data and clock recovery) is a Digital
Signal Processor designed to extract the data and recover
the clock from a digitized CVBS signal.
22.1.4
DATA STANDARDS AND CLOCK RATES
The data standards and clock rates that can be recovered
are shown in Table 22.
Table 22 Data standards and clock rates
22.1.5
DATA CAPTURE TIMING
The Data Capture timing section uses the synchronisation
information extracted from the CVBS signal to generate
the required horizontal and vertical reference timings.
The timing section automatically recognizes and selects
the appropriate timings for either 625 (50 Hz)
synchronisation or 525 (60 Hz) synchronisation.
A TXT12.VIDEO SIGNAL QUALITY flag is set when the
timing section is locked correctly to the incoming CVBS
signal. When TXT12.VIDEO SIGNAL QUALITY is set,
another flag TXT12.525/625 SYNC can be used to identify
the standard.
22.1.6
ACQUISITION
The acquisition section extracts the relevant information
from the serial stream of data from the MulVIP and stores
it in memory.
22.1.6.1
Making a page request
A page is requested by writing a series of bytes into the
TXT3.PRD<4:0> SFR, which corresponds to the number
of the page required. The bytes written into TXT3 are
stored in a RAM with an auto-incrementing address. The
start address for the RAM is set using the TXT2.SC<2:0>
(to define which part of the page request is being written)
and TXT2.REQ<3:0> (along with TXT2.ACQ BANK) is
used to define which of the 12 page request blocks is
being modified.
If TXT2.REQ<3:0> is greater than 09H, then data being
written to TXT3 is ignored (applies to Bank 0 and Bank 1).
Table 23 shows the contents of the page request RAM.
Up to 12 pages of Teletext can be acquired on the 12 page
device, when TXT1.EXT PKT OFF is set to logic 1, and up
to 10 pages can be acquired when this bit is set to logic 0.
Table 23 The contents of the Page request RAM
If the ‘Do Care’ bit for part of the page number is set to
logic 0, then that part of the page number is ignored when
the Teletext decoder is deciding whether a page being
received off-air should be stored or not. For example, if the
‘Do Care’ bits for the four subcode digits are all set to
logic 0, then every subcode version of the page will be
captured.
DATA STANDARD
CLOCK RATE
625 WST
6.9375 MHz
525 WST
5.7272 MHz
VPS
5.0 MHz
WSS
5.0 MHz
Closed Caption
500 kHz
START
COLUMN
PRD4
PRD3
PRD2
PRD1
PRD0
0
Do Care
Magazine
HOLD MAG2 MAG1 MAG0
1
Do Care
Page Tens
PT3
PT2
PT1
PT0
2
Do Care
Page Units
PU3
PU2
PU1
PU0
3
Do Care
Hour Tens
X
HT1
HT0
4
Do Care
Hours
Units
HU3
HU2
HU1
HU0
5
Do Care
Minutes
Tens
X
MT2
MT1
MT0
6
Do Care
Minutes
Units
MU3
MU2
MU1
MU0
7
X
XXE1
E0
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