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參數(shù)資料
| 型號： | SAA5667HL/NNNN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 30/112頁 |
| 文件大?。?/td> | 537K |
| 代理商： | SAA5667HL/NNNN |
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2004 Sep 03
24
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
AA
Assert Acknowledge ag. When this bit is set, an acknowledge is returned
after any one of the following conditions:
Own slave address is received
General call address is received (S1ADR.GC = 1)
A data byte is received, while the device is programmed to be a master receiver
A data byte is received, while the device is selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own address or general call address is received.
I2C-bus Data Register (S1DAT)
DAT7 to DAT0
I2C-bus data
I2C-bus Status Register (S1STA)
STAT4 to STAT0
I2C-bus interface status
Software ADC Register (SAD)
VHI
analog input voltage greater than DAC voltage (logic 1)
CH1 to CH0
ADC input channel select bits; CH<1:0>:
00 = ADC3
01 = ADC0
10 = ADC1
11 = ADC2
initiate voltage comparison between ADC input channel and SAD value
SAD7 to SAD4
4 MSBs of DAC input word
Software ADC Control Register (SADB)
DC_COMP
enable DC comparator mode (logic 1)
SAD3 to SAD0
4 LSBs of SAD value
Stack Pointer (SP)
SP7 to SP0
stack pointer value
Timer/counter Control Register (TCON)
TF1
Timer 1 overow ag. Set by hardware on Timer/counter overow. Cleared by
hardware when processor vectors to interrupt routine.
TR1
Timer 1 run control bit. Set/cleared by software to turn Timer/counter on/off.
TF0
Timer 0 overow ag. Set by hardware on Timer/counter overow. Cleared by
hardware when processor vectors to interrupt routine.
TR0
Timer 0 run control bit. Set/cleared by software to turn Timer/counter on/off.
IE1
Interrupt 1 edge ag. Both edges generate ag. Set by hardware when external
interrupt edge detected. Cleared by hardware when interrupt processed.
IT1
Interrupt 1 type control bit. Set/cleared by software to specify edge/low level
triggered external interrupts.
IE0
Interrupt 0 Edge l ag. Set by hardware when external interrupt edge detected.
Cleared by hardware when interrupt processed.
IT0
Interrupt 0 type ag. Set/cleared by software to specify falling edge/low level
triggered external interrupts.
BITS
FUNCTION
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