參數(shù)資料
型號(hào)： SAA5667HL/NNNN
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 29/112頁(yè)
文件大?。?/td> 537K
代理商： SAA5667HL/NNNN
2004 Sep 03
23
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
TI
Is the transmit interrupt ag. Set by hardware at the end of the 8th bit time in
Mode 0, or at the beginning of the stop bit in the other modes. Must be cleared
by software.
RI
Is the receive interrupt ag. Set by hardware at the end of the 8th bit time in
Mode 0, or halfway through the stop bit time in the other modes, in any serial
reception (except see SM2). Must be cleared by software.
I2C-bus Slave Address Register (S1ADR)
ADR6 to ADR0
I2C-bus slave address to which the device will respond
GC
enable I2C-bus general call address (logic 1)
I2C-bus Control Register (S1CON)
CR2 to CR0
clock rate bits; CR<2:0>: (for nominal mode)
000 = 200 kHz bit rate
001 = 7.5 kHz bit rate
010 = 300 kHz bit rate
011 = 400 kHz bit rate
100 = 50 kHz bit rate
101 = 3.75 kHz bit rate
110 = 75 kHz bit rate
111 = 100 kHz bit rate
ENSI
enable I2C-bus interface (logic 1)
STA
START ag. When this bit is set in slave mode, the hardware checks the I2C-bus
and generates a START condition if the bus is free or after the bus becomes free.
If the device operates in master mode, it will generate a repeated START
condition.
STO
STOP ag. If this bit is set in a master mode, a STOP condition is generated. A
STOP condition detected on the I2C-bus clears this bit. This bit may also be set
in slave mode, to recover from an error condition. In this case, no STOP
condition is generated to the I2C-bus, but the hardware releases the SDA and
SCL lines and switches to the not selected receiver mode. The STOP ag is
cleared by the hardware.
SI
Serial Interrupt ag. This ag is set and an interrupt request is generated, after
any of the following events occur:
A START condition is generated in master mode
The own slave address has been received during AA = 1
The general call address has been received while S1ADR.GC and AA = 1
A data byte has been received or transmitted in master mode (even if arbitration
is lost)
A data byte has been received or transmitted as selected slave
A STOP or START condition is received as selected slave receiver or
transmitter. While the SI ag is set, SCL remains LOW and the serial transfer is
suspended. SI must be reset by software.
BITS
FUNCTION
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