參數(shù)資料
型號(hào)： SAA5667HL/NNNN
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 57/112頁(yè)
文件大小： 537K
代理商： SAA5667HL/NNNN
2004 Sep 03
49
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
18.4
UART baud rates
For full details of the UART operation please refer to
“Handbook IC20,80C51-Based 8-bit Microcontrollers”.
Remark: fclk used refers to the microcontroller clock
frequency (12 MHz). The SAA56xx family of devices uses
both clock edges, so the division factor is 6 instead of 12.
The serial port can operate with different baud rates,
depending on its mode.
Mode 0 (SM0 = 0, SM1 = 0); in shift register mode the
baud rate is fixed at 1
6fclk
Mode 2 (SM0 = 0, SM1 = 1); in this fixed baud rate
mode, the baud rate is determined by the SMOD bit in
the PCON register: baud rate =
Modes 1 (SM0 = 0, SM1 = 1); and 3 (SM0 = 1,
SM1 = 0); in these modes the baud rate is variable and
is determined by either Timer 1 or Timer 2; see
Section 13.
Timer 1: can be used in either Timer or Counter mode,
when the baud rate is determined by the timer overflow
rate and the value of SMOD as follows:
baud rate =
i.e.
baud rate =
where T1H is
the decimal value of the register contents.
When Timer 1 is configured for timer operation, it is normal
to use the 8-bit auto-reload mode, however 16-bit mode
can be used for very low baud rates. In this case the
Timer 1 interrupt will need to do a 16-bit software reload.
Timer 2: will be placed in Baud generator mode when
RCLK0 and/or TCLK0 bits in the T2CON register are set.
When Timer 2 is clocked internally it has the following
baud rate:
.
Where TH2 and TL2 is the decimal value of the 16-bit
contents of there respective SFRs.
When Timer 2 is configured as a counter, using pin T2 the
baud rate equals the Timer 2 overflow rate divided by 16.
19 LED SUPPORT
Port pins P0.5 and P0.6 have an 8 mA current sinking
capability to enable LEDs in series with current limiting
resistors to be driven directly, without the need for
additional buffering circuits.
20 EXTERNAL SRAM/ROM INTERFACE
The external address/data bus of the 80C51
microprocessor may be interfaced to:
Additional SRAM Data memory for multi-page
acquisition applications
External Program ROM.
The application circuit can be achieved using either the
multiplexed address and data I/O or the de-multiplexed
address and data I/O.
External SRAM Data Memory: it is possible to interface
up to 256 kbytes of external data memory using pins
RAMBK<1:0> and A15_BK. Each of the four Data memory
banks is selected by RAMBK<1:0> (SFR ROMBK<4:3>),
see Table 20.
Figure 12 shows an example of the interfacing
connections for external SRAM data memory; see also
Section 30.
Table 20 RAMBK selection
External program ROM (pin EA tied LOW): the internal
microcontroller logic makes it possible to only address
192 bytes of external program ROM with linear
addressing. Figure 13 shows the interface connections.
Remark: For emulating the external program ROM pins
A15_BK, ROMBK0, ROMBK1 and ROMBK2 are used to
address up to 256 kbytes. With additional glue logic these
address lines can be used to address up to 256 kbytes os
external ROM. Figure 14 shows the additional glue logic.
2
SMOD
32
------------------
f
clk
×
2
SMOD
32
------------------
Timer 1 overflow rate
×
2
SMOD
32
------------------
f
clk
6
256
T1H
–
()
×
------------------------------------------
×
f
clk
16
65536
TH2, TL2
()
–
[]
×
----------------------------------------------------------------------
RAMBK<1:0>
BANK
EXTERNAL
ADDRESS RANGE
00
Bank 0
0 to 64 kbytes
01
Bank 1
64 to 128 kbytes
10
Bank 2
128 to 192 kbytes
11
Bank 3
192 to 256 kbytes
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