參數(shù)資料
型號(hào): SAA5667HL/NNNN
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù): 7/112頁(yè)
文件大?。?/td> 537K
代理商: SAA5667HL/NNNN
2004 Sep 03
104
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
30.1.2
APPLICATION NOTES
Ports AD0 to AD7 of the microcontroller can be connected
to pins D0 to D7 of the SRAM in any order.
For the addressing, the lower group of address lines
(A0 to A8) and the upper group of address lines
(A9 to A14, A15_BK, RAMBK0 and RAMBK1) may be
connected in any order within the groups, provided that the
full 256 kbytes of external SRAM is used.
Fig.43 shows the application diagram for multipage.
When using an external SRAM smaller than 256 kbytes,
the relevant number of bits from the microcontroller
address bus should be disconnected, always removing the
most significant bits first.
For power saving modes, it might be advisable to control
the CE pin of the SRAM module(s) using one of the
microcontroller ports to de-select the SRAM.
30.1.3
EXTERNAL DATA MEMORY ACCESS
Table 46 External data memory access
See Figs. 44 and 45.
Note
1. The external SRAM is intended to be used with the
multipage software, therefore only the 12 MHz clock
microcontroller timings are provided.
30.1.3.1
Symbol explanations
Each timing symbol has five characters. The first character
is always ‘t’ (time). Depending on their positions, the other
characters indicate the name of a signal or the logical
status of that signal. The designations are:
A = Address
C = Clock
D = Input data
H = Logic level HIGH
I = Instruction (program memory contents)
L = Logic level LOW, or ALE
P = PSEN
Q = Output data
R = RD signal
t = Time
V = Valid
W = WR signal
X = No longer a valid logic level
Z = Float
Examples:
tAVLL = Time for address valid to ALE LOW.
tLLPL = Time for ALE to PSEN LOW.
SYMBOL
PARAMETER
TYPICAL(1) UNIT
tRLRH
RD pulse width
250
ns
tWLWH
WR pulse width
250
ns
tRLDV
RD LOW to valid data in 198
ns
tRHDX
Data hold after RD
0
ns
tLLWL
ALE LOW to RD or
WR LOW
132
ns
tAVWL
Address valid to WR
LOW or RD LOW
172
ns
tQVWX
Data valid to WR LOW
89
ns
tWHQX
Data hold after WR
15
ns
tWHLH
RD or WR HIGH to
ALE HIGH
40
ns
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