參數(shù)資料
型號(hào)： RB5C396
廠商： RICOH COMPANY LTD
元件分類： 總線控制器
英文描述： PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2
中文描述： PCMCIA BUS CONTROLLER, PBGA256
封裝： 23 X 23 MM, PLASTIC, BGA-256
文件頁(yè)數(shù)： 72/93頁(yè)
文件大?。?/td> 449K
代理商： RB5C396
RF5C296/RF5C396L/RB5C396/RF5C396
68
The GPI pin, as its full name “general-purpose input pin” suggests, functions as an input pin for general purpose
use. Further, it can also be connected to the VS1# pin on the PC card slot to detect the 5V PC card. (For details, see
“3.2 5VDET/GPI and VS1# Pins” in “3. Connections to PCMCIA Slot” in “HARDWARE DESIGN CONSIDERA-
TIONS”.)
· Interface Status Register (Index : 01h) : bit7
This bit can be used to specify reading back the 5VDET/GPI pin.
· Card Status Change Register (Index : 04h) : bit4 (GPI Change Bit)
This bit will be set to “1” upon generation of interrupts derived from the GPI pin status change when bit2
(GPI Enable Bit) is set to “1” in the Card Detect and General Control Register (Index : 16h).
· Card Detect and General Control Register (Index : 16h) : bit3 (GPI Transmission Control Bit)
This bit can be set to “1” and “0” to specify generation of interrupts upon transition of the GPI pin from “H” to
“L” and vice versa, respectively.
· Card Detect and General Control Register (Index : 16h) : bit2 (GPI Enable Bit)
This bit can be used to enable interrupts from the GPI pin and set to “1” to specify generation of interrupts
upon the GPI input status change.
The internal registers described below function as those relating to the READY#/BUSY# pin status on the condi-
tion that the PC card is the memory card.
· Interface Status Register (Index : 01h) : bit5 (Ready/Busy# Bit)
This bit can be set to “0” and “1” to specify reading back the READY#/BUSY# pins, respectively (specify read-
ing back the IREQ# pin when the PC card is the I/O card).
· Card Status Change Register (Index : 04h) : bit2 (Ready Change Bit)
This bit will be set to “1” upon transition of the READY#/BUSY# pins from “L” to “H”.
· Card Status Interrupt Configuration Register (Index : 05h) : bit2 (Ready Enable Bit)
This bit can be set to “1” to specify generation of interrupts upon transition of the READY#/BUSY# pins from
“L” to “H”.
5.5 READY#/BUSY# Pins
5.4 5VDET/GPI Pin
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