參數(shù)資料
型號(hào)： RB5C396
廠商： RICOH COMPANY LTD
元件分類： 總線控制器
英文描述： PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2
中文描述： PCMCIA BUS CONTROLLER, PBGA256
封裝： 23 X 23 MM, PLASTIC, BGA-256
文件頁(yè)數(shù)： 61/93頁(yè)
文件大?。?/td> 449K
代理商： RB5C396
RF5C296/RF5C396L/RB5C396/RF5C396
57
06h : bit6 06h : bit7
07h : bit1 07h : bit5
Index
Index
Index
Index
Index
Index
Index
Index
07h : bit3 07h : bit7
0Bh : bit7 to 0 0Fh : bit7 to 0
0Ah : bit7 to 0 0Eh : bit7 to 0
37h : bit7 to 0 39h : bit7 to 0
36h : bit7 to 0 38h : bit7 to 0
The memory address space occupies 16MB ranging from “000000h” to “0FFFFFFh” on the ISA bus. On the con-
trary, the memory address space occupies 64MB ranging from “0000000h” to “3FFFFFFh” on the PC card bus.
The RF5C296 and the RF5C396 are capable of mapping any given five memory address windows (ranges) on the
ISA bus to the memory address windows on the PC card bus in units of 4kB for each PC card slot. On the ISA bus,
each memory address window ranges from the starting address specified by the System Memory Address n
Mapping Start High/Low Byte Registers to the ending address specified by the System Memory Address n
Mapping Stop High/Low Byte Registers. On the PC card bus, each memory address window equals to its equiva-
lent on the ISA bus plus the setting of the Card Memory Offset Address n Low Byte Register (forming a two's com-
plement number).
I/O Address Window Setting
Start Address
Stop Address
Off Set Address
(Only RF5C396)
Wait State
Zero Wait State
Data Size
IOCS16# Source
Enable
Window 0
Window 1
09h : bit7 to 0 0Dh : bit7 to 0
08h : bit7 to 0 0Ch : bit7 to 0
07h : bit2 07h : bit6
07h : bit0 07h : bit4
These bits can be used to specify the ending address of the applicable I/O address window.
These bits can be used to specify the offset address of the applicable I/O address window.
These bits can be used to specify the one wait state (4SYSCLK) 16bit I/O cycle and the stan-
dard 16bit I/O cycle when set to “1” and “0”, respectively. The 16bit I/O cycle is unavailable
in zero wait state form.
These bits can be used to specify the zero wait state 8bit I/O cycle rendering the ZEROWS#
pin signal active and the standard 8bit I/O cycle when set to “1” and “0”, respectively.
These bits can be used to specify the 8bit mode and the 16bit mode when set to “0” and “1”,
respectively.
These bits can be used to specify the dependence of the IOCS16# pin signal on the IOIS16# pin
signal from the PC card and on the Data Size Bit when set to “1” and “0”, respectively.
These bits can be used to specify rendering the applicable I/O window active when set to “1”.
These bits can be used to specify the starting address of the applicable I/O address window.
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