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參數(shù)資料
| 型號： | RB5C396 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2 |
| 中文描述： | PCMCIA BUS CONTROLLER, PBGA256 |
| 封裝： | 23 X 23 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 69/93頁 |
| 文件大?。?/td> | 449K |
| 代理商： | RB5C396 |
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RF5C296/RF5C396L/RB5C396/RF5C396
65
Interrupts derived from the IRQn pins represent different output waveforms in the Level Mode and the Edge
Mode. In the Level Mode, the IRQn pin outputs are caused to transition from high impedance to “L” upon interrupt
generation and vice versa upon completion of interrupt processing. In the Edge Mode, the IRQn pin outputs are
caused to transition from low level to “H” upon interrupt generation and vice versa upon completion of interrupt pro-
cessing. The Level Mode and the Edge Mode can be specified by setting bit1 (Level Mode Interrupt Enable Bit) to
“1” and “0”, respectively, in the Global Control Register (Index : 1Eh).
Of the IRQn pin outputs, the IRQ14 pin output alone allows exceptional waveform control, which can be specified
by setting bit3 (IRQ14 Pulse Mode Enable Bit) to “1” in the Global Control Register (Index : 1Eh). Namely, inter-
rupts derived from the IRQ14 pin represent output waveforms in the Level Mode even when the Edge Mode is spec-
ified by setting bit1 (Level Mode Interrupt Enable Bit) to “0” in the Global Control Register (Index : 1Eh).
Meanwhile, the INTR# pin output is caused to transition from high level to “L” for the duration of three clock
pulses upon interrupt generation and vice versa upon completion of interrupt processing.
Interrupts derived from the IREQ# pin can be canceled by first canceling interrupts on the PC card bus with the
IREQ# pin caused to transition to low level and then canceling interrupts on the ISA bus with the IREQ# pin caused
to transition to “H”.
Interrupts derived from the PC card status change can be canceled by the following two methods :
(1) Reading the Card Status Change Register (Index : 04h)
(2) Setting applicable bits to “1” in the Card Status Change Register (Index : 04h) provided that bit2 (Explicit Write
Back Card Status Change Acknowledge Bit) is set to “1” in the Global Control Register (Index : 1Eh).
The RF5C296 and the RF5C396 have the function of indicating the status of the pins on the PC card slot in vari-
ous forms to the CPU. This function falls into the following four types :
(1) Reading back the pins on the PC card slot
(2) Making settings upon occurrence of any pin status change on the PC card slot
(3) Generating interrupts upon occurrence of any pin status change on the PC card slot
(4) Performing other processes upon occurrence of any pin status change on the PC card slot
The internal registers contained in the RF5C296 and the RF5C396 are grouped according to their functions to
facilitate such processes as interrupt processing. While the internal registers are described in detail under classifi-
cation by function in “INTERNAL REGISTERS”, they are described briefly under classification by pin on the PC
card slot in this section.
5. Card Slot Pin Status Indication and Register Setting
4.3 Control over Interrupt Cancellation
4.2 Control over Interrupt Output Waveforms
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