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參數(shù)資料
| 型號： | RB5C396 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2 |
| 中文描述： | PCMCIA BUS CONTROLLER, PBGA256 |
| 封裝： | 23 X 23 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 47/93頁 |
| 文件大?。?/td> | 449K |
| 代理商： | RB5C396 |
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RF5C296/RF5C396L/RB5C396/RF5C396
43
Index : 39h
Default value : 0000 0000b
Read & Write
bit7 : offset address 15
bit6 : offset address 14
bit5 : offset address 13
bit4 : offset address 12
bit3 : offset address 11
bit2 : offset address 10
bit1 : offset address 9
bit0 : offset address 8
Index : 3Ah
Default value : 32h (RF5C296), B2h (RF5C396)
Read only register, 32h is read back from RF5C296, B2h is read back from RF5C396.
Read Only
Index : 3Bh
Default value : 0000 0000b
Read & Write
bit7to bit2 : Reserved.
bit1
: DMA Mode Enable Bit.
When this bit is set to “1”, the DMA Mode is selected in which DMA-related signals are redefined as
described in “DMA Mode”. This bit defaults to “0”. This bit cannot be set to “1” simultaneously for
Slot #0 and Slot #1.
bit0
: PCMCIA Interface Disable Bit.
If this bit is set to “1”, signals shown in the below table are set to “Z”, all PCMCIA interface signals are
disabled and become “Z”. The built-in pull-down resistor is disabled for data bus signals. Slot output sig-
nals will be caused to transition to high impedance even when bit 0 is set in the Power and RESETDRV
Control Register.
Input
Output
CD1#, CD2#, BVD1, BVD2, RDY/BSY#, WAIT#, WP, INPACK#
CA[25 : 0], CD[15 : 0], CE1#, CE2#, CIORD#, CIOWR#, OE#, REG#, RESET, WE#
5.6 Mode Control Register 3
5.5 Chip Identification Register (Read Only)
5.4 Card I/O Offset Address 1 High Byte Register
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