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參數(shù)資料
| 型號： | RB5C396 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2 |
| 中文描述： | PCMCIA BUS CONTROLLER, PBGA256 |
| 封裝： | 23 X 23 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 51/93頁 |
| 文件大?。?/td> | 449K |
| 代理商： | RB5C396 |
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RF5C296/RF5C396L/RB5C396/RF5C396
47
1.2 INTR# Pin
The INTR# pin determines whether to use external decoding or internal decoding for access to the internal reg-
isters. Pulling up and down the INTR# pin specifies internal decoding and external decoding, respectively. For
details, see “6. Access to Internal Registers” in “FUNCTIONAL DESCRIPTION”.
Basically, connections to the ISA bus only require connections to corresponding bus pins.
The IOCS16#, MEMCS16#, ZEROWS#, and IOCHRDY pins are open-drain output pins which require an external
pull-up resistor in the absence of any pull-up resistor provided on the ISA bus. These resistors are designed to drive
a 300
pull-up resistor (for the IOCS16#, MEMCS16#, and ZEROWS# pins) and a 1k
pull-up resistor (for the
IOCHRDY).
The ZEROWS# and IOCHRDY pins are also caused to transition to “H” level for the maximum duration of one
clock pulse upon transition from low level to high impedance as shown in the figure below. Originally, strict regula-
tion of the pull-up resistor for these open-drain output pins is required for the fast rising edge of their pin signals but
not recommended in consideration of current consumption.
For the RF5C296 and the RF5C396, such unique designs of the ZEROWS# and IOCHRDY pins allow restriction
of current consumption without strict regulation of the pull-up resistor to such a degree as not to affect any other
system.
The CS# pin is intended to determine an I/O address for access to the control registers for the RF5C296 and the
RF5C396 and not directly related to access to the card windows.
As described before, either external decoding or internal decoding can be used to determine an I/O address for
access to the control registers. (For details, see “6. Access to Internal Registers” in “FUNCTIONAL DESCRIP-
TION”.)
When external decoding is used, an I/O address for access to the control registers can be determined by decod-
ing the address signals output from the SA15 to the SA1 (or the SA23 to the SA16 for some systems) for input with
negative logic to the CS# pin.
When internal decoding is used, access to the internal registers is conditional upon the CS# pin held at “L” and
an I/O address of 03E0h or 03E1h. In this case, the CS# pin must receive a signal input which becomes active only
when the SA15 to SA10 pins are all caused to transition to “L”. This is because the status of the CE# pin affects the
Power Down Mode (specified by bit0 in the Global Control Register (Index : 1Eh)). When the Power Down Mode is
not in use, therefore, the CE# pin should be held at “L”.
IOCHRDY
One clock pulse
T21
ZEROWS#
SYSCLK
2. Connections to System Bus
2.2 CS# Pin
2.1 IOCS16#, MEMCS16#, ZEROWS#, and IOCHRDY Pins
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