參數(shù)資料
型號(hào)： RB5C396
廠商： RICOH COMPANY LTD
元件分類(lèi)： 總線控制器
英文描述： PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2
中文描述： PCMCIA BUS CONTROLLER, PBGA256
封裝： 23 X 23 MM, PLASTIC, BGA-256
文件頁(yè)數(shù)： 36/93頁(yè)
文件大小： 449K
代理商： RB5C396
RF5C296/RF5C396L/RB5C396/RF5C396
32
Index : 1Eh
Default value :
′′′′
0000b
Read &Write
This register is not duplicated per slot. This register can be accessed from either Slot#0 or Slot1# in RF5C396.
Consequently, access to indexes of 1Eh and 5Eh means access to the same register.
bit7 to bit4 : Reserved
bit3
: IRQ14 Pulse Mode Enable. Setting this bit to “1” and bit 1 (Level Mode Interrupt Enable) to “0” will
enable the RF5C296/RF5C396 to support pulse-mode IRQ14 interrupt output.
: Explicit Write Back Card Status Change Acknowledge Bit. Setting this bit to “1” will require an explicit
write of “1” to the Card Status Change Register Bit which indicates an interrupting condition. Default
value is “0”. When this bit is set to “0”, the card status change interrupt is acknowledged by reading the
Card Status Change Register, and the register bits are cleared upon a read.
: In the Level Mode, the IRQn pin signals are held at high impedance until generation of any interrupt
caused by the Card Status Change Register (Index : 04h) or routed by the IRQn pin signals from the
I/O card. When this bit is set to “1”, the IRQn pin signals are caused to transition from high impedance to “0”
upon interrupt generation and reverted to high impedance upon completion of interrupt processing (in the
Level Mode). When this bit is set to “0”, the IRQn pin signals are caused to transition from “1” to “0”
upon interrupt enabling and from “0” to “1” upon interrupt generation, and becomes inactive upon completion
of interrupt processing (in the Edge Mode).
: Power Down Bit
If this bit is set to “1”, then setting CS# to “1” will go into the power down mode. During CS# controlled
power down, all internal registers are inaccessible, outputs are disabled, and the chip is at minimum
power consumption level. IRQn and RI_OUT# will still be active to monitor the card detect and RI#
status for resume indication.
bit2
bit1
bit0
CS#
0
1
0
1
Power Down Control Bit
0
0
1
1
Power Down Mode
No
No
No
Yes
1.6 Global Control Register
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