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參數(shù)資料
| 型號： | RB5C396 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2 |
| 中文描述： | PCMCIA BUS CONTROLLER, PBGA256 |
| 封裝： | 23 X 23 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 18/93頁 |
| 文件大?。?/td> | 449K |
| 代理商： | RB5C396 |
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RF5C296/RF5C396L/RB5C396/RF5C396
14
Symbol
Function
Pin No.
RF5C296 RF5C396*
2
CD1#, CD2#
RDY/BSY#
(IREQ#)
REG#
WAIT#
WP
(IOIS16#)
RESET
INPACK#
Card Detect Input 1 & 2*
3
READY/BUSY# input on the memory PC card,
and IREQ# input on the I/O card.
When this signal is “L” memory access is limited
to Attribute memory. During normal access for
I/O, this signal must be kept “L”. During DMA
cycle, this signal must be kept “H”.
This pin may also be used as card side DACK in
DMA mode.
Bus Cycle Wait Input from PC Card
Write Protect switch input on the memory PC
card and, IOIS16# is asserted by PC card when
the I/O cycle is 16bit on the I/O.
This pin may also be used as card side DREQ in
DMA mode.
Card Reset Output
Input Acknowledge. “L” is output to INPACK# on
the PCMCIA bus only when I/O ports accessed
during I/O signal read are enabled on PC cards
that support this signal.
When INPACK# signal is enabled for
RF5C296/RF5C396, I/O signal read data will be
output to the system only when the INPACK#
signal is enabled. This pin may also be used as
card side DREQ in DMA mode.
10,70
39
8
55
69
51
16
Slot#0:10,69
Slot#1:73,132
Slot#0:39
Slot#1:101
Slot#0:8
Slot#1:71
Slot#0:54
Slot#1:116
Slot#0:68
Slot#1:131
Slot#0:51
Slot#1:114
Slot#0:56
Slot#1:119
I/O*
1
I
I
O(TS)
I
I
O(TS)
I
*
1) I : Input, O : Output, I/O : Input/Output, O (TS) : Tri-State Output.
*
2) All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1).
For example, ACA25 to ACA0 are the card address buses to the slot #0.
Pin No. of the RB5C396 differ from those of others. Refer to "PIN CONFIGURATION".
*
3) CD1# and CD2# are powered by VCC_AT instead of VCC_SLOT because hot plug-in/out is supported during card slot power is off.
Drive
—
—
4mA
—
—
4mA
—
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