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參數(shù)資料
| 型號(hào)： | RB5C396 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2 |
| 中文描述： | PCMCIA BUS CONTROLLER, PBGA256 |
| 封裝： | 23 X 23 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 35/93頁(yè) |
| 文件大小： | 449K |
| 代理商： | RB5C396 |
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RF5C296/RF5C396L/RB5C396/RF5C396
31
Interrupt and General Control (Index : 03h) (except INTR# enable bit)
Address Window Enable (Index : 06h) (except MEMCS16# Decode A23 to A12 bit)
I/O Control (Index : 07h)
I/O Address n Start Low Byte (Index : 08h, 0Ch)
I/O Address n Start High Byte (Index : 09h, 0Dh)
I/O Address n Stop Low Byte (Index : 0Ah, 0Eh)
I/O Address n Stop High Byte (Index : 0Bh, 0Fh)
System Memory Address n Mapping Start Low Byte (Index : 10h, 18h, 20h, 28h, 30h)
System Memory Address n Mapping Start High Byte (Index : 11h, 19h, 21h, 29h, 31h)
System Memory Address n Mapping Stop Low Byte (Index : 12h, 1Ah, 22h, 2Ah, 32h)
System Memory Address n Mapping Stop High Byte (Index : 13h, 1Bh, 23h, 2Bh, 33h)
Card Memory Offset Address n Low Byte (Index : 14h,1Ch, 24h, 2Ch, 34h)
Card Memory Offset Address n High Byte (Index : 15h,1Dh, 25h, 2Dh, 35h)
bit0 : 16bit memory delay inhibit. Default value is “0”. If this bit is set to “0”, the falling edge of the control strobes
OE# and WE# will be generated from the first falling edge of SYSCLK after the falling edge of MEMW# or
MEMR# in the 16bit memory cycle. If this bit is set to “1”, the control strobes OE# and WE# will not be syn-
chronously delayed by SYSCLK.
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