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參數(shù)資料
| 型號： | RB5C396 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2 |
| 中文描述： | PCMCIA BUS CONTROLLER, PBGA256 |
| 封裝： | 23 X 23 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 67/93頁 |
| 文件大小： | 449K |
| 代理商： | RB5C396 |
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RF5C296/RF5C396L/RB5C396/RF5C396
63
Interrupts derived from the IREQ# pin particularly for the I/O card can be assigned to the IRQn pins as their out-
put destinations by setting bits3 to 0 in the Interrupt and General Control Register (Index : 03h) as shown in the first
table on the next page.
Interrupts derived from the PC card status change for both the I/O card and the memory card can be assigned
to the IRQn pins or the INTR# pin as their output destinations by setting bits7 to 4 in the Card Status Interrupt
Configuration Register (Index : 05h) or bit4 (INTR# Enable Bit) in the Interrupt and General Control Register
(Index : 03h) as shown in the second table on the next page.
Incidentally, the IRQn pins are caused to transition to high impedance unless assigned as interrupt output desti-
nations.
As described above, interrupts derived from the CD1# and/or CD2# pin status change among interrupts derived
from the PC card status change can be assigned to the RI_OUT# pin as their output destination.
More specifically, the RI_OUT# pin output can be generated upon occurrence of the CD1# and/or CD2# pin sta-
tus change by setting bit4 (Card Detect Resume Enable Bit) to “1” in the Card Detect and General Control Register
(Index : 16h) and then setting bit3 (Card Detect Enable Bit) to “1” in the Card Status Interrupt Configuration
Register (Index : 05h). For details on these registers, see their respective description in “INTERNAL REGISTERS”.
4.1 Control over Interrupt Output Destinations
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