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參數(shù)資料
| 型號： | PSD913F1V |
| 英文描述： | 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging |
| 中文描述： | Flash在系統(tǒng)可編程微控制器外設(shè) |
| 文件頁數(shù)： | 78/94頁 |
| 文件大?。?/td> | 463K |
| 代理商： | PSD913F1V |
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Preliminary
PSD913F1
77
-15
-20
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
26
30
Address Setup Time
(Note 1)
10
12
ns
Address Hold Time
(Note 1)
12
14
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
20
25
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
t
WHAX1
CS Valid to Leading Edge of WR
(Note 3)
20
25
ns
WR Data Setup Time
(Note 3)
45
50
ns
WR Data Hold Time
(Note 3)
8
10
ns
WR Pulse Width
(Note 3)
48
53
ns
Trailing Edge of WR to Address Invalid
(Note 3)
12
17
ns
t
WHAX2
Trailing Edge of WR to DPLD Address
Input Invalid
(Notes 3 and 6)
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
45
50
ns
t
WLMV
WR Valid to Port Output Valid Using
Micro
Cell Register Preset/Clear
Data Valid to Port Output Valid
Using Micro
Cell Register Preset/Clear
Address Input Valid to Address
Output Delay
(Notes 3 and 4)
90
100
ns
t
DVMV
(Notes 3 and 5)
90
100
ns
t
AVPV
(Note 2)
48
55
ns
Write, Erase and Program Timing
(3.0 V to 3.6 V Versions)
NOTES:
1. Any input used to select an internal PSD913F1 function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Microcontroller Interface – PSD913F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
NOTE:
1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
-15
-20
TURBO
OFF
Slew
(Note 1)
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
PD
PLD Input Pin/Feedback to
PLD Combinatorial Output
48
55
Add 20 Sub 6
ns
t
ARD
PLD Array Delay
29
33
ns
PLD Combinatorial Timing
(3.0 V to 3.6 V Versions)
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| PSD913F2 | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads |
| PSD913F2V | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging |
| PSD913F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913F1V-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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