參數(shù)資料
型號(hào)： PSD913F1V
英文描述： 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging
中文描述： Flash在系統(tǒng)可編程微控制器外設(shè)
文件頁(yè)數(shù)： 48/94頁(yè)
文件大?。?/td> 463K
代理商： PSD913F1V
Preliminary
PSD913F1
47
The
PSD913F1
Functional
Blocks
(cont.)
Control
Register
Setting
at Run-Time
Direction
Register
Setting
at Run-Time
Defined In
PSDsoft
Mode
MCU I/O
Declare pins only
0
1=output,
0=input,
PLD I/O
Logic or chip
select equations
NA
Data Port
(Port A)
Selected for MCU
with non-mux bus
NA
NA
Address Out
(Port A,B)
Declare pins only
1
1
Address In
(Port A,B,C,D)
Declare pins only
NA
NA
JTAG ISP
Declare pins only
NA
NA
Table 18. Port Operating Mode Settings
*
NA = Not Applicable
9.4.2.1 MCU I/OMode
In the MCU I/O Mode, the microcontroller uses the PSD913F1 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD913F1 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing a
‘
0
’
to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding
bit in the Direction Register. See the subsection on the Direction Register in the
“
Port
Registers
”
section. When the pin is configured as an output, the content of the Data Out
Register drives the pin. When configured as an input, the microcontroller can read the port
input through the Data In buffer.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/OMode
The PLD I/O Mode uses a port as an input to the PLDs, and/or as an output from the
GPLD. The corresponding bit in the Direction Register must not be set to
‘
1
’
if the pin is
defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified in PSDsoft by declar-
ing the port pins, and then specifying an equation in PSDsoft.
相關(guān)PDF資料
PDF描述
PSD913F2 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913F1V-12B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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