參數(shù)資料
型號(hào)： PSD913F1V
英文描述： 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging
中文描述： Flash在系統(tǒng)可編程微控制器外設(shè)
文件頁數(shù)： 26/94頁
文件大小： 463K
代理商： PSD913F1V
Preliminary
PSD913F1
25
The
PSD913F1
Functional
Blocks
(cont.)
9.1.1.7.1 Data Polling
Polling on DQ7 is a method of checking whether a Program or Erase instruction is in
progress or has completed. Figure 5 shows the Data Polling algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD913F1 begins. The MCU then reads the location of the byte to be programmed in Flash
to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the
original data byte to be programmed. The MCU continues to poll this location, comparing
DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of the original
data, and the Error bit at DQ5 remains
‘
0
’
, then the embedded algorithm is complete.
If the Error bit at DQ5 is
‘
1
’
, the MCU should test DQ7 again since DQ7 may have changed
simultaneously with DQ5 (see Figure 5).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a
‘
1
’
to a bit
that was not erased (not erased is logic
‘
0
’
).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the byte that was written to Flash with
the byte that was intended to be written.
When using the Data Polling method after an erase instruction, Figure 5 still applies.
However, DQ7 will be
‘
0
’
until the erase operation is complete. A
‘
1
’
on DQ5 will indicate
a timeout failure of the erase operation, a
‘
0
’
indicates no error. The MCU can read any
location within the sector being erased to get DQ7 and DQ5.
PSDsoft will generate ANSI C code functions which implement these Data Polling
algorithms.
Figure 5. Data Polling Flow Chart
START
READ DQ5 & DQ7
at VALID ADDRESS
YES
YES
YES
NO
NO
NO
=
DATA7
DQ5
=1
=
DATA
READ DQ7
FAIL
PASS
相關(guān)PDF資料
PDF描述
PSD913F2 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913F1V-12B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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