參數(shù)資料
型號(hào)： PSD913F1V
英文描述： 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging
中文描述： Flash在系統(tǒng)可編程微控制器外設(shè)
文件頁(yè)數(shù)： 16/94頁(yè)
文件大?。?/td> 463K
代理商： PSD913F1V
Preliminary
PSD913F1
15
9.0
The
PSD913F1
Functional
Blocks
As shown in Figure 1, the PSD913F1 consists of six major types of functional blocks:
J
Memory Blocks
J
PLD Blocks
J
Bus Interface
J
I/OPorts
J
Power Management Unit
J
JTAG Interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
9.1 Memory Blocks
The PSD913F1 has the following memory blocks:
The main Flash memory
Secondary EEPROM memory
SRAM.
The memory select signals for these blocks originate from the Decode PLD (DPLD) and
are user-defined in PSDsoft.
Table 8 summarizes the PSD913F1 memory blocks.
Device
Main Flash
EEPROM
SRAM
PSD913F1
128KB
32KB
2KB
Table 8. Memory Blocks
9.1.1 Main Flash and Secondary EEPROM
The 1 Mbit main Flash memory block is divided evenly into eight 16 Kbyte sectors. The
EEPROM memory is divided into four sectors of eight Kbytes each. Each sector of either
memory can be separately protected from program and erase operations.
Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte.
Flash sector erasure may be suspended while data is read from other sectors of memory
and then resumed after reading.
EEPROM may be programmed byte-by-byte or sector-by-sector, and erasing is automatic
and transparent. The integrity of the data can be secured with the help of Software Data
Protection (SDP). Any write operation to the EEPROM is inhibited during the first five
milliseconds following power-up.
During a program or erase of Flash, or during a write of the EEPROM, the status can be
output on the Rdy/Bsy pin of Port C3. This pin is set up using PSDsoft.
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