參數(shù)資料
型號(hào)： PSD913F1V
英文描述： 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging
中文描述： Flash在系統(tǒng)可編程微控制器外設(shè)
文件頁(yè)數(shù)： 18/94頁(yè)
文件大?。?/td> 463K
代理商： PSD913F1V
Preliminary
PSD913F1
17
The
PSD913F1
Functional
Blocks
(cont.)
9.1.1.3.1 Instructions
An instruction is defined as a sequence of specific operations. Each received byte is
sequentially decoded by the PSD and not executed as a standard write operation. The
instruction is executed when the correct number of bytes are properly received and the time
between two consecutive bytes is shorter than the time-out value. Some instructions are
structured to include read operations after the initial write operations.
The sequencing of any instruction must be followed exactly. Any invalid combination of
instruction bytes or time-out between two consecutive bytes while addressing Flash
memory will reset the device logic into a read array mode (Flash memory reads like a ROM
device). An invalid combination or time-out while addressing the EEPROM block will cause
the offending byte to be interpreted as a single operation.
The PSD913F1 supports these instructions (see Table 9):
Flash memory:
J
Erase memory by chip or sector
J
Suspend or resume sector erase
J
Program a byte
J
Reset to read array mode
J
Read Flash Identifier value
J
Read sector protection status
EEPROM:
J
Write data to OTP Row
J
Read data from OTP Row
J
Power down memory
J
Enable Software Data Protect (SDP)
J
Disable SDP
J
Return from read OTP Row read mode or power down mode.
These instructions are detailed in Table 9. For efficient decoding of the instructions, the first
two bytes of an instruction are the coded cycles and are followed by a command byte or
confirmation byte. The coded cycles consist of writing the data AAh to address X555h
during the first cycle and data 55h to address XAAAh during the second cycle. Address
lines A15-A12 are don’t cares during the instruction write cycles. However, the appropriate
sector select signal (FSi or EESi) must be selected.
相關(guān)PDF資料
PDF描述
PSD913F2 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913F1V-12B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F1V-12M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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