參數(shù)資料
型號: PSD913F1V
英文描述: 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging
中文描述: Flash在系統(tǒng)可編程微控制器外設(shè)
文件頁數(shù): 51/94頁
文件大?。?/td> 463K
代理商: PSD913F1V
PSD913F1
Preliminary
50
The
PSD913F1
Functional
Blocks
(cont.)
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port D
NA
NA
NA
NA
NA
Slew
Rate
Slew
Rate
Slew
Rate
Table 23. Drive Register Pin Assignment
NOTE:
NA = Not Applicable.
9.4.3.3 Drive Select Register
The Drive Select Register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is
set to a
1
. The default pin drive is CMOS.
Aside:
the slew rate is a measurement of the rise and fall times of an output. A higher slew
rate means a faster output response and may create more electrical noise. A pin operates
in a high slew rate when the corresponding bit in the Drive Register is set to
1
. The default
rate is slow slew.
Table 23 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can
be configured as Open Drain outputs and which pins the slew rate can be set for.
相關(guān)PDF資料
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