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參數資料
| 型號： | PSD913F1V |
| 英文描述： | 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging |
| 中文描述： | Flash在系統(tǒng)可編程微控制器外設 |
| 文件頁數： | 72/94頁 |
| 文件大小： | 463K |
| 代理商： | PSD913F1V |
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Preliminary
PSD913F1
71
-90
-12
-15
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
20
22
28
Address Setup Time
(Note 1)
6
8
10
ns
Address Hold Time
(Note 1)
8
9
11
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
20
25
30
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
CS Valid to Leading Edge of WR
(Note 3)
25
30
35
ns
WR Data Setup Time
(Note 3)
35
40
45
ns
WR Data Hold Time
(Note 3)
5
5
5
ns
WR Pulse Width
(Note 3)
35
40
45
ns
t
WHAX1
Trailing Edge of WR to Address
Invalid
(Note 3)
8
9
10
ns
t
WHAX2
Trailing Edge of WR to DPLD
Address Input Invalid
(Notes 3 and 4)
0
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
30
35
38
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note 2)
25
28
30
ns
Write Timing
(5 V ± 10% Versions)
NOTES:
1.
Any input used to select an internal PSD913F1 function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
2.
3.
4.
Microcontroller Interface – PSD913F1 AC/DC Parameters
(5V ±10% Versions)
NOTE:
1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
-90
-12
-15
TURBO Slew
OFF
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
(Note 1)
Unit
PLD Input Pin/Feedback
to PLD Combinatorial
Output
t
PD
25
30
32
Add 10 Sub 2
ns
t
ARD
PLD Array Delay
16
18
22
ns
PLD Combinatorial Timing
(5 V ± 10%)
相關PDF資料 |
PDF描述 |
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| PSD913F2 | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads |
| PSD913F2V | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging |
| PSD913F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng)) |
| PSD934F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng)) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD913F1V-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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