參數(shù)資料
型號: PSD913F1V
英文描述: 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging
中文描述: Flash在系統(tǒng)可編程微控制器外設(shè)
文件頁數(shù): 63/94頁
文件大小: 463K
代理商: PSD913F1V
PSD913F1
Preliminary
62
The
PSD913F1
Functional
Blocks
(cont.)
Port C Pin
PC0
PC1
PC3
PC4
PC5
PC6
JTAG Signals
TMS
TCK
TSTAT
TERR
TDI
TDO
Description
Mode Select
Clock
Status
Error Flag
Serial Data In
Serial Data Out
Table 30. JTAG Port Signals
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD913F1 can be enabled on Port C (see Table 30). All
memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG interface. A blank part can be mounted on a printed circuit
board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
*
SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
**
Port Configuration
MCU I/O
PLD Output
Power On Reset
Input Mode
Valid after internal
PSD configuration
bits are loaded
Tri-stated
Tri-stated
Warm Reset
Input Mode
Valid
Power Down Mode
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Not defined
Tri-stated
Address Out
Data Port
Tri-stated
Tri-stated
Table 29. Status During Power On Reset, Warm Reset and Power Down Mode
Register
Power On Reset
Cleared to
0
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to
0
Warm Reset
Unchanged
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to
0
Power Down Mode
Unchanged
Unchanged
PMMR0, 2
VM Register*
All other registers
Unchanged
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note 54 for more details on JTAG In-System-Programming.
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