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參數資料
| 型號： | PSD913F1V |
| 英文描述： | 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA57163SE with Standard Packaging |
| 中文描述： | Flash在系統(tǒng)可編程微控制器外設 |
| 文件頁數： | 50/94頁 |
| 文件大小： | 463K |
| 代理商： | PSD913F1V |
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Preliminary
PSD913F1
49
The
PSD913F1
Functional
Blocks
(cont.)
9.4.3 Port Configuration Registers (PCRs)
Each port has a set of PCRs used for configuration. The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 7. The addresses in Table 7 are the offsets in hex from the base of the
CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
shown in Table 20, are used for setting the port configurations. The default power-up state
for each register in Table 20 is 00h.
Register Name
Port
MCU Access
Control
Direction
Drive Select*
A,B
A,B,C,D
A,B,C,D
Write/Read
Write/Read
Write/Read
Table 20. Port Configuration Registers
*
NOTE:
See Table 27 for Drive Register bit definition.
9.4.3.1 Control Register
Any bit set to
‘
0
’
in the Control Register sets the corresponding Port pin to MCU I/O Mode,
and a
‘
1
’
sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B
have an associated Control Register.
9.4.3.2 Direction Register
The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to
‘
1
’
in the Direction Register will cause the corresponding pin to be an output, and any bit set
to
‘
0
’
will cause it to be an input. The default mode for all port pins is input.
Figures 22 and 23 show the Port Architecture diagrams for Ports A, B and C, respectively.
The direction of data flow for Ports A, B, and C are controlled by the direction register.
An example of a configuration for a port with the three least significant bits set to output and
the remainder set to input is shown in Table 22. Since Port D only contains three pins, the
Direction Register for Port D has only the three least significant bits active.
Direction Register Bit
0
1
Port Pin Mode
Input
Output
Table 21. Port Pin Direction Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Table 22. Port Direction Assignment Example
相關PDF資料 |
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| PSD913F2 | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads |
| PSD913F2V | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging |
| PSD913F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng)) |
| PSD934F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng)) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD913F1V-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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