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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 70/78頁 |
| 文件大?。?/td> | 610K |
| 代理商： | PENTIUM III |
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70
Datasheet
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
BR0#
BR1#
I/O
I
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor pins. The table below gives the rotating interconnect between
the processor and bus signals.
BSEL[1:0]
I/O
These signals are used to select the system bus frequency. A BSEL[1:0] = “01”
selects a 100 MHz system bus frequency and a BSEL[1:0] = “11” selects a 133 MHz
system bus frequency. The frequency is determined by the processor(s), chipset,
and frequency synthesizer capabilities. All system bus agents must operate at the
same frequency. The Pentium III processor for the PGA370 socket operates at 100
MHz and 133 MHz system bus frequencies. Individual processors will only operate
at their specified front side bus (FSB) frequency. Either 100 MHz or 133 MHz, not
both.
On motherboards which support operation at either 66 MHz or 100 MHz, a
BSEL[1:0] = “x0” will select a 66 Mhz system bus frequency. 66 MHz operation is not
support by the Pentium III processor for the PGA370 socket; therefore, BSEL0 is
ignored.
These signals must be pulled up to 2.5 V or 3.3V with 1 K
resistors and provided
as a frequency selection signal to the clock driver/synthesizer. If the system
motherboard is not capable of operating at 133 MHz, it should ground the BSEL1
signal and generate a 100 MHz system bus frequency. See
Section 2.8.2
for
implementation examples.
CLKREF
I
The CLKREF input is a filtered 1.25V supply voltage for the processor PLL. A
voltage divider and decoupling solution is provided by the motherboard. See the
design guide for implementation details.
Table 33. Signal Description (Sheet 3 of 8)
Name
Type
Description
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its
symmetric agent ID. All agents then configure their pins to match the appropriate bus
signal protocol, as shown below.
BR[1:0]# Signal Agent IDs
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
Pin Sampled Active in RESET#
Agent ID
BR0#
0
BR1#
3
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