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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 50/78頁 |
| 文件大?。?/td> | 610K |
| 代理商： | PENTIUM III |
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50
Datasheet
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
5.2
Processor Markings
The following figure exemplifies the processor top-side markings and it is provided to aid in the
identification of an Pentium
III
processor for the PGA370 socket.
Table 27
lists the measurements
for the package dimensions.
5.3
Processor Signal Listing
Table 29
and
Table 30
provide the processor pin definitions. The signal locations on the PGA370
socket are to be used for signal routing, simulation, and component placement on the baseboard.
Figure 21
provides a pin-side view of the Pentium
III
processor pin-out.
The following notes apply to
Table 29
and
Table 30
:
NOTES:
1. These pins are required for backwards compatibility with other Intel processors. They are not used by the
Pentium III processor. Refer to the appropriate platform design guide and
Section 7.1
for implementation
details.
2. RESET# signal must be connected to pins AH4 and X4 for backwards compatibility. Refer to the appropriate
platform design guide and
Section 7.1
for implementation details. If backwards compatibility is not required,
then RESET2# (X4) should be connected to GND.
3. VCC
V must be supplied by the same voltage source supplying the V
TT
pins.
4. These V
TT
pins must be left unconnected (N/C) for backwards compatibility with Intel
Celeron processors
(CPUID 066xh). For designs which do not support the Intel Celeron processors (CPUID 066xh), and for
compatibility with future processors, these V
TT
pins should be connected to the V
TT
plane. Refer to the
appropriate platform design guide and
Section 7.1
for implementation details. For dual processor designs,
these pins must be connected to V
TT
.
5. This pin is required for backwards compatibility. If backwards compatibility is not required, this pin may be left
connected to V
CC
. Refer to the appropriate platform design guide for implementation details.
6. Previously, PGA370 designs defined this pin as a GND. It is now reserved and must be left unconnected
(N/C).
7. Previously, PGA370 socket designs defined this pin as a GND. It is now CLKREF.
8. For Uniprocessor designs, this pin is not used and it is defined as RESERVED. Refer to the Peniutm
III
processor Specification Updatefor a complete listing of processors that support DP operation.
Figure 20. Top Side Processor Markings
Dynamic Production Mark Example
RB80526PY550266
FFFFFFFF-0001 SSSSS
FPO # - S/N
S-spec#
pentium
III
logo
MALAY
intel
i (m) (c) ’99
Static Mark ink printed at
substrate supplier
Country of Origin
Dynamic Laser Mark
Swatch
Product Code
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