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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 16/78頁 |
| 文件大小： | 610K |
| 代理商： | PENTIUM III |
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16
Datasheet
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
2.3.1
Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL. Please refer to the Phase Lock Loop Power section in
the
appropriate platform design guide
for the recommended filter specifications.
2.4
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in
Table 6
. Failure to do so can result in timing
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot).
Unlike SC242 based designs, motherboards utilizing the PGA370 socket
must provide high frequency decoupling capacitors on all power planes for the processor.
2.4.1
Processor V
CC
CORE
Decoupling
The regulator for the V
CCCORE
input must be capable of delivering the dI
CCCORE
/dt (defined in
Table 6
) while maintaining the required tolerances (also defined in
Table 6
). Failure to meet these
specifications can result in timing violations (during V
CCCORE
sag) or a reduced lifetime of the
component (during V
CCCORE
overshoot).
2.4.2
Processor System Bus AGTL+ Decoupling
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL+ bus operation. See the AGTL+ buffer specification in the
Intel
Pentium
II
Processor Developer's Manual
for more information. Also, refer to the appropriate platform design
guide for recommended capacitor component placement.
Figure 5. Processor V
CCCMOS
Package Routing
Intel
Pentium
III
Processor
0.1 uF
2.5V Supply
2.5V
1.5V Supply
1.5V
VCC
CMOS
*ICH or
Other Logic
CMOS
Pullups
CMOS Signals
Note: *Ensure this logic is compatible
with 1.5V signal levels of the
Intel
Pentium
III processor
for the PGA370 socket.
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