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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 11/78頁 |
| 文件大小： | 610K |
| 代理商： | PENTIUM III |
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Datasheet
11
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
2.0
Electrical Specifications
2.1
Processor System Bus and V
REF
The Pentium
III
processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology.
The Intel
Pentium
Pro processor system bus specification is similar to the GTL specification,
but was enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the GTL specification, and is referred to as GTL+. For more
information on GTL+ specifications, see the GTL+ buffer specification in the
Intel
Pentium
II
Processor Developer’s Manual
.
Current P6 family processors vary from the Intel
Pentium Pro processor in their output buffer
implementation. The buffers that drive the system bus signals on the Intel
Celeron
TM
, Pentium II,
and Pentium
III
processors are actively driven to V
CCCORE
for one clock cycle after the low to high
transition to improve rise times. These signals should still be considered open-drain and require
termination to a supply that provides the high signal level. Because this specification is different
from the standard GTL+ specification, it is referred to as AGTL+, or Assisted GTL+ in this and
other documentation. AGTL+ logic and GTL+ logic are compatible with each other and may both
be used on the same system bus. For more information on AGTL+ routing, see the appropriate
platform design guide.
AGTL+ inputs use differential receivers which require a reference signal (V
REF
). V
REF
is used by
the receivers to determine if a signal is a logical 0 or a logical 1, and is supplied by the motherboard
to the PGA370 socket for the processor core. Local V
REF
copies should also be generated on the
motherboard for all other devices on the AGTL+ system bus. Termination (usually a resistor at
each end of the signal trace) is used to pull the bus up to the high voltage level and to control
reflections on the transmission line. The processor contains on-die termination resistors that
provide termination for one end of the AGTL+ bus, except for RESET#. These specifications
assume another resistor at the end of each signal trace to ensure adequate signal quality for the
AGTL+ signals and provide backwards compatibility for the Intel Celeron processor; see
Table 9
for the bus termination voltage specifications for AGTL+. Refer to the
Intel
Pentium
II
Processor Developer’s Manual
for the AGTL+ bus specification. Solutions exist for single-ended
termination as well, though this implementation changes system design and eliminate backwards
compatibility for Intel Celeron processors in the PPGA package. Single-ended termination designs
must still provide an AGTL+ termination resistor on the motherboard for the RESET# signal.
Figure 2
is a schematic representation of the AGTL+ bus topology for the Pentium
III
processors in
the PGA370 socket.
Figure 3
is a schematic representation of the AGTL+ bus topoplogy in a dual-
processor configuration with Pentium
III
processors in the PGA370 socket.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus including trace lengths is highly recommended when designing a system with a heavily
loaded AGTL+ bus, especially for systems using a single set of termination resistors (i.e., those on
the processor die). Such designs will not match the solution space allowed for by installation of
termination resistors on the baseboard.
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