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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 20/78頁 |
| 文件大小： | 610K |
| 代理商： | PENTIUM III |
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20
Datasheet
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
NOTES:
1. See
Section 7.0
for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See
Section 7.0
for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for Vcc
CMOS
(1.5 V for the Pentium III
processor) operation.
4. These signals are 2.5 V tolerant.
5. V
CC
is the power supply for the processor core and is described in
Section 2.6
.
VID[3:0] is described in
Section 2.6
.
V
TT
is used to terminate the system bus and generate V
REF
on the motherboard.
V
SS
is system ground.
V
CC
,
V
CC
,
Vcc
are described in
Section 2.3
.
BSEL[1:0] is described in
Section 2.8.2
and
Section 7.0
.
All other signals are described in
Section 7.0
.
6. RESET# must always be terminated to V
TT
on the motherboard, on-die termination is not provided for this
signal.
7. This signal is not supported by all processors. Refer to the Pentium
III Processor Specification Updatefor a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pulldown resistor value.
2.8.1
Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP
signals are synchronous to TCK.
Table 3. System Bus Signal Groups
1
Group Name
Signals
AGTL+ Input
BPRI#, BR1#
7
, DEFER#, RESET#
6
, RS[2:0]#, RSP#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#
2
, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
CMOS Input
3
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
CMOS Input
4
PWRGOOD
CMOS Output
3
FERR#, IERR#, THERMTRIP#
System Bus
Clock
4
BCLK
APIC Clock
4
PICCLK
APIC I/O
3
PICD[1:0]
TAP Input
3
TCK, TDI, TMS, TRST#
TAP Output
3
TDO
Power/Other
5
BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
THERMDN, THERMDP, RTTCTRL
8
, V
COREDET
, VID[3:0], V
CC1.5
,
V
CC2.5
,
V
CCCMOS
,
V
CC
CORE
, V
REF
, V
SS
, V
TT
, Reserved
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