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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 25/78頁 |
| 文件大?。?/td> | 610K |
| 代理商： | PENTIUM III |
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Datasheet
25
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All specifications in this table apply only to the Pentium
III
processor. For motherboard compatibility with the
Intel
Celeron
TM
processor, see the Intel
Celeron
TM
Processor Datasheet.
3. Vcc
and Icc
supply the processor core and the on-die L2 cache.
4. Use the “typical voltage” specification with the “tolerance specifications” to provide correct voltage regulation
to the processor.
5. V
TT
and Vcc
must be held to 1.5V ±9% while the AGTL+ bus is active. It is required that V
TT
and Vcc
be
held to 1.5V ±3% while the processor system bus is static (idle condition). The ±3% range is the required
design target; ±9% will come from the transient noise added. This is measured at the PGA370 socket pins on
the bottom side of the baseboard.
6.
These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the
processor socket pin on the soldered-side of the motherboard.
V
CC
must return to within the static
voltage specification within 100
μ
s after a transient event; see the VRM 8.4 DC-DC Converter Design
Guidelinesfor further details.
7. V
should be generated from V
TT
by a voltage divider of 1% resistors or 1% matched resistors. Refer to the
Intel
Pentium
II Processor Developer’s Manual for more details on V
.
8. Maximum I
CC
is measured at V
CC
typical voltage and under a maximum signal loading conditions.
9. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of Vcc
(Vcc
). In this case, the maximum current level for the regulator, Icc
, can be reduced from
the specified maximum current Icc
CORE _MAX
and is calculated by the equation:
Icc
CORE_REG
= Icc
CORE_MAX
×
(Vcc
CORE_TYP
- Vcc
CORE_STATIC_TOLERANCE
) / Vcc
CORE_TYP
10.The current specified is the current required for a single processor. A similar amount of current is drawn
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is
used (see
Section 2.1
).
11.The current specified is also for AutoHALT state.
12.Maximum values are specified by design/characterization at nominal Vcc
.
13.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
14.dIcc/dt specifications are measured and specified at the PGA370 socket pins.
15.CLKREF must be held to 1.25V ±6.5%. This tolerance accounts for a ±5% power supply and ±1% resistor
divider tolerance. It is recommended that the motherboard generate the CLKREF reference from either the
2.5V or 3.3V supply. V
TT
should not be used due to risk of AGTL+ switching noise coupling to this analog
reference.
16.Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output
load ranges specified in the tables above.
17.FMB - Flexible Motherboard recommendation
18.This specification applies to PGA370 processors operating at frequencies of 933MHz or higher.
19.Vcc=1.65V for cB0 Core Stepping (CPUID 0683h); Vcc=1.60V for cA2 Core Stepping (CPUID 0681h).
I
DSLP
I
CC
Deep Sleep for
processor core
2.2
A
dI
CC
CORE
/dt
Power supply current
slew rate
240
A/μs
12, 13, 14
dI
v
TT
/dt
Termination current
slew rate
8
A/μs
12, 13, See
Table 9
Table 6. Voltage and Current Specifications
1, 2
(Sheet 2 of 2)
Symbol
Parameter
Core Freq
Min
Typ
Max
Unit
Notes
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