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| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 37/78頁 |
| 文件大?。?/td> | 610K |
| 代理商： | PENTIUM III |
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Datasheet
37
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
3.2
AGTL+ Signal Quality Specifications and Measurement
Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the appropriate platform design guide. Refer to the
Intel
Pentium
II Processor
Developer's Manual
(Order Number 243502) for the AGTL+ buffer specification.
Table 18
provides the AGTL+ signal quality specifications for the processor for use in simulating
signal quality at the processor pins.
The Pentium
III
processor for the PGA370 socket maximum allowable overshoot and undershoot
specifications for a given duration of time are detailed in
Table 20
through
Table 22
.
Figure 15
shows the AGTL+ ringback tolerance and
Figure 16
shows the overshoot/undershoot waveform.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. Specifications are for the edge rate of 0.3 - 0.8V/ns. See
Figure 15
for the generic waveform.
3. All values specified by design characterization.
4. Please see
Table 20
for maximum allowable overshoot.
5. Ringback between V
+ 100 mV and V
+ 200 mV or V
- 200 mV and V
- 100 mVs requires the
flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (Intel
Pentium
II
Developers Manual). Ringback below V
+ 100 mV or above V
REF
- 100 mV is not supported.
6. Intel recommends simulations not exceed a ringback value of V
REF
sources of system noise.
7. A negative value for
ρ
indicates that the amplitude of ringback is above V
REF
. (i.e.,
φ
= -100 mV specifies the
signal cannot ringback below V
+ 100 mV).
8.
φ
and
ρ
: are measured relative to V
REF
.
α
: is measured relative to V
REF
+ 200 mV.
Figure 14. BCLK, PICCLK Generic Clock Waveform at the Processor Pins
V2
V1
V3
V3
V4
V5
Table 18. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor
Pins
1, 2, 3
T# Parameter
Min
Unit
Figure
Notes
α
: Overshoot
τ
: Minimum Time at High
ρ
: Amplitude of Ringback
φ
: Final Settling Voltage
δ
: Duration of Squarewave Ringback
100
mV
15
4, 8
0.50
ns
15
±200
mV
15
5, 6, 7, 8
200
mV
15
8
N/A
ns
15
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