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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 19/78頁 |
| 文件大?。?/td> | 610K |
| 代理商： | PENTIUM III |
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Datasheet
19
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
2.7
Processor System Bus Unused Pins
All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins
to V
CCCORE
, V
REF
, V
SS
, V
TT
,
or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors. See
Section 5.3
for a pin listing of the
processor and the location of each RESERVED pin.
PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to
V
CCCMOS
even when the APIC will not be used. A separate pull-up resistor must be provided for
each PICD signal.
For reliable operation, always connect unused inputs or bidirectional signals to their deasserted
signal level. The pull-up or pull-down resistor values are system dependent and should be chosen
such that the logic high (V
IH
) and logic low (V
IL
) requirements are met. See
Table 8
for DC
specifications of non-AGTL+ signals.
Unused AGTL+ inputs must be properly terminated to V
TT
on PGA370 socket motherboards
which support the Intel Celeron and the Pentium
III
processors. For designs that intend to only
support the Pentium
III
processor, unused AGTL+ inputs will be terminated by the processor’s on-
die termination resistors and thus do not need to be terminated on the motherboard. However,
RESET# must always be terminated on the motherboard as the Pentium
III
processor for the
PGA370 socket does not provide on-die termination of this AGTL+ input.
For unused CMOS inputs, active low signals should be connected through a pull-up resistor to
V
CCCMOS
and meet V
IH
requirements. Unused active high CMOS inputs should be connected
through a pull-down resistor to ground (V
SS
) and meet V
IL
requirements. Unused CMOS outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
2.8
Processor System Bus Signal Groups
To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require a
high-level source provided termination resistors. However, the Pentium
III
processor for the
PGA370 socket includes on-die termination.
Motherboard designs that also support
Intel Celeron processors in the PPGA package will need to provide AGTL+ termination on
the system motherboard as well. Platform designs that support dual processor configurations
will need to provide AGTL+ termination, via a termination package, in any socket not
populated with a processor.
AGTL+ input signals have differential input buffers which use V
REF
as a reference signal. AGTL+
output signals require termination to 1.5 V. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other
CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and
STPCLK#) are only 1.5 V tolerant and must be pulled up to V
CCCMOS
. The CMOS, APIC, and
TAP outputs are open drain and must be pulled high to V
CCCMOS
. This ensures correct operation
for current Intel Pentium
III
and Intel Celeron processors.
The groups and the signals contained within each group are shown in
Table 3
. Refer to
Section 7.0
for a description of these signals.
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