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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 32/78頁 |
| 文件大小： | 610K |
| 代理商： | PENTIUM III |
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32
Datasheet
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.75 V at the processor pins. All
TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 1.5 V.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Note:
For
Figure 7
through
Figure 13
, the following apply:
1.
Figure 7
through
Figure 13
are to be used in conjunction with
Table 10
through
Table 16
.
2. All AC timings for the AGTL+ signals at the processor pins are referenced to the BCLK rising
edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V
at the processor pins.
3. All AC timings for the APIC I/O signals at the processor pins are referenced to the PICCLK
rising edge at 1.25 V. All APIC I/O signal timings are referenced at 0.75 V at the processor
pins.
4. All AC timings for the TAP signals at the processor pins are referenced to the TCK rising edge
at 0.75 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor
pins.
Table 16. System Bus AC Specifications (TAP Connection)
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T30: TCK Frequency
16.667
MHz
T31: TCK Period
60.0
ns
7
T32: TCK High Time
25.0
ns
7
V
REF
+ 0.200V,
10
V
REF
- 0.200V,
10
T33: TCK Low Time
25.0
ns
7
T34: TCK Rise Time
5.0
ns
7
(V
REF
- 0.200V) -
(V
REF
+ 0.200V),
4, 10
T35: TCK Fall Time
5.0
ns
7
(V
REF
+ 0.200V) -
(V
REF
- 0.200V),
4, 10
T36: TRST# Pulse Width
40.0
ns
13
Asynchronous,
10
T37: TDI, TMS Setup Time
5.0
ns
12
5
T38: TDI, TMS Hold Time
14.0
ns
12
5
T39: TDO Valid Delay
1.0
10.0
ns
12
6, 7
T40: TDO Float Delay
25.0
ns
12
6, 7, 10
T41: All Non-Test Outputs Valid Delay
2.0
25.0
ns
12
6, 8, 9
T42: All Non-Test Inputs Setup Time
25.0
ns
12
6, 8, 9, 10
T43: All Non-Test Inputs Setup Time
5.0
ns
12
5, 8, 9
T44: All Non-Test Inputs Hold Time
13.0
ns
12
5, 8, 9
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