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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15017EJ2V0UD
If A, X, B, C, AX, or BC is described in an instruction that specifies r, r’, rp, or rp’ in the operand column, the
A, X, B, C, AX, or BC instruction code generates the instruction code that specifies the following registers based
on the operand of the RSS pseudo instruction in RA78K4.
Register
RSS = 0
RSS = 1
A
R1
R5
X
R0
R4
B
R3
R7
C
R2
R6
AX
RP0
RP2
BC
RP1
RP3
If R0 to R7 and RP0 to RP4 are specified in r, r’, rp, and rp’ in the operand column, an instruction code that
conforms to the specification is output. (Instruction code that directly describes A or AX in the operand column
is not output.)
The A, B, and C registers that are used in indexed addressing and based indexed addressing cannot be
described as R1, R3, R2, or R5, R7, R6.
(3) Cautions on use
Switching the RSS bit obtains the same effect as holding two register sets. However, be careful and write the
program so that implicit descriptions in the program and dynamically changing the RSS bit during program
execution always agree.
Also, since a program with RSS = 1 cannot be used in a program that uses context switching, the portability of
the program becomes poor. Furthermore, since different registers having the same name are used, the readability
of the program worsens, and debugging becomes difficult. Therefore, when RSS = 1 must be used, write the
program while taking these problems into consideration.
A register that does not have the RSS bit set can be accessed by specifying the absolute name.