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User’s Manual U15017EJ2V0UD
CHAPTER 9 WATCHDOG TIMER
The watchdog timer detects runaway programs.
Program or system errors are detected by the generation of watchdog timer interrupts. Therefore, at each location
in the program, the instruction that clears the watchdog timer (starts the count) within a constant time is input.
If the watchdog timer overflows without executing the instruction that clears the watchdog timer within the set period,
a watchdog timer interrupt (INTWDT) is generated to signal a program error.
9.1 Configuration
Figure 9-1 shows a block diagram of the watchdog timer.
Figure 9-1. Block Diagram of Watchdog Timer
Cautions 1. When a standby mode (HALT/STOP/IDLE) is selected during operation of the watchdog timer,
the watchdog timer is cleared and stopped. If a request is made to clear the HALT/IDLE
standby mode, the watchdog timer starts operating immediately after the request is issued.
If a request is made to clear the STOP standby mode, the watchdog timer starts operating
once the oscillation stabilization time elapses after the request is issued.
2. INTWDT is a non-maskable interrupt, while INTWDTM is a maskable interrupt. Whether to
use the watchdog timer interrupt as non-maskable or maskable can be specified using bit
1 (SWDT) of the interrupt select control register (SNMI). For an explanation of this register,
refer to Section 16.3.6 of CHAPTER 16 INTERRUPT FUNCTION.
Remark
f
CLK
: Internal system clock (f
XX
to f
XX
/8)
Watchdog timer
f
CLK
f
CLK
/2
21
f
CLK
/2
20
f
CLK
/2
19
f
CLK
/2
17
INTWDT/INTWDTM
Clear signal
HALT
IDLE
STOP
Set bit 7 (RUN) of the
watchdog timer mode
register (WDM) to 1.
S