
29
CHAPTER 1 GENERAL
User
’
s Manual U15017EJ2V0UD
1.6 Functional Outline
Part Number
μ
PD784975A
μ
PD78F4976A
Item
Internal memory
ROM
Mask ROM
Flash memory
96 KB
128 KB
Note
Peripheral RAM
3,072 bytes
4,608 bytes
High-speed RAM
512 bytes
VFD display RAM
96 bytes
General-purpose register
8 bits
×
16 registers
×
8 banks, or 16 bits
×
8 registers
×
8 banks
Minimum instruction execution time
160 ns (@f
XX
= 12.5 MHz operation)
Instruction set
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
I/O port
(including VFD-multiplexed pins)
Total:
CMOS input:
CMOS I/O:
N-ch open-drain I/O:
P-ch open-drain I/O:
P-ch open-drain output:
72 pins
12 pin
20 pins
8 pins
24 pins
8 pins
VFD controller/driver
Total display output:
Display current 10 mA:
Display current: 3 mA:
48 pins
16 pins
32 pins
A/D converter
8-bit resolution
×
12 channels
Supply voltage: AV
DD
= 4.5 to 5.5 V
Serial interface
3-wire serial I/O mode:
UART/IOE (3-wire serial I/O): 1 channel
2 channels
Timer
16-bit timer/event counter:
8-bit PWM timer:
Watch timer:
Watchdog timer:
1 channel
2 channels
1 channel
1 channel
Timer output
2 pins (8-bit PWM output)
Vectored
interrupt source
Maskable
Internal: 14, external: 3, internal/external: 2
Non-maskable
Internal: 1
Software
BRK, BRKCS instructions, operand error
Supply voltage
V
DD
= 4.5 to 5.5 V
Package
100-pin plastic QFP (14
×
20)
Note
96 KB can be selected by the memory size switching register (IMS)